Rtl Designer

ACL Digital

5 - 10 years

20 - 30 Lacs

bengaluru

Posted:15 hours ago| Platform:

Apply

Skills Required

soc design low power design vclp upf rtl design ptpx

Work Mode

Work from Office

Job Type

Full Time

Job Description

Were Hiring – RTL Design / Low-Power Verification Engineer (UPF / VCLP Expert)

RTL Design

ACL Digital

Location:

What You’ll Do

Define, develop, and validate
Unified Power Format (UPF)
for multi-voltage, power-gated
SoC/ASIC
designs.
Perform
power intent verification
using
Synopsys VC LP / PrimeTime PX / Cadence CLP
.
Analyze and close
VCLP warnings and errors
— isolation, retention, and level shifter strategies.
Collaborate with
RTL & PD teams
to ensure correct low-power cell integration.
Support
dynamic low-power simulation
(VCS LP / Xcelium LP).
Drive
power-aware STA
and
power-up/power-down sequencing
validation.
Contribute to
power signoff
before tape-out.

What We’re Looking For

Hands-on experience with
RTL Design
,
UPF
, and
Low-Power SoC Methodologies
.
Proficiency in
Verilog/SystemVerilog
,
TCL/Python/Perl
scripting.
Familiarity with
Synopsys
or
Cadence low-power toolchains
.
Strong understanding of
isolation, retention, and level-shifter techniques
.
Excellent debugging, analytical, and communication skills.

Be part of a team that designs tomorrow’s semiconductors, today!

Apply Now:

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