15 Ptpx Jobs

Role Overview: You have 12+ years of experience in Digital ASIC/Processor Design with strong fundamentals in core areas such as Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology. Your communication skills are excellent, enabling you to collaborate effectively with design teams globally. Key Responsibilities: - Lead, train, and mentor a team of junior engineers for a large modem design project in advanced process nodes - Collaborate with RTL, DFT, and PD leads to take a project from Post-RTL to Netlist release, focusing on area, timing, power, and testability - Write timing constraints, conduct synthesis, formal verification, CLP, Primetime, PTPX, and CECO tasks -...

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

As a VLSI Design Engineer at MarvyLogic, you will be responsible for the design and integration of ARM-based processor SOC and subsystem. Your role will involve utilizing your solid experience in digital VLSI design and ensuring a good understanding of Multi-processor and cache designs. Your hands-on coding experience in Verilog/VHDL will be essential for this position. Additionally, familiarity with various ARM AMBA protocols such as AXI, AHB, and cache coherency protocols is required. Key Responsibilities: - Design and integration of ARM-based processor SOC and subsystem - Utilize solid experience in digital VLSI design - Ensure a good understanding of Multi-processor and cache designs - H...

As an experienced Power Modeling and Estimation Engineer, you will be responsible for developing and driving a framework for highly optimized, modular, and scalable SoCs. Your primary focus will be on power analysis, power optimization, simulation, and roll-ups. You will utilize tools such as PTPX/Power artist and other industry-standard power estimation tools to achieve these objectives. Collaborating with various SoC and IP teams, you will work on power projections, requirements, silicon power capture, and correlation with pre-si estimates. Additionally, you will perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power ...

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

Qualcomm India Private Limited is seeking a Senior or Lead Hardware Engineer with 3-5 years of experience in Power fundamentals, PTPX, CLP, design verification, RTL coding, synthesis, physical design, as well as protocol knowledge of DDR, CHI, Cache, computer organization, and bus protocol. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering experience, or a Master's degree with 2+ years of experience, or a PhD with 1+ year of experience. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. In c...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will h...

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexiti...

Qualcomm India Private Limited is seeking an individual to join the Engineering Group, specifically in the Hardware Engineering department. As part of this role, you will be responsible for creating power specifications for Qualcomm DSP IPs based on the design specifications provided. Your tasks will include developing power intent using UPF for DSP IPs, as well as validating power intent at both RTL level and Gate level (synthesis, PD) using CLP. In addition, you will be required to fix any power intent issues based on PA DV feedback and debug problems related to MV cell insertion during synthesis by modifying UPF accordingly. Another aspect of the role involves projecting dynamic and leaka...

Creating power specifications for Qualcomm DSP IPs based on the design specifications is a key responsibility in this role at Qualcomm India Private Limited. You will be required to develop power intent using UPF for DSP IPs based on the power specifications provided. Additionally, you will need to validate the power intent at RTL level and Gate level (synthesis, PD) using CLP. In case of any issues related to power intent, you will be responsible for fixing them based on PA DV feedback. Another aspect of the role involves debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly. You will also be tasked with projecting dynamic and leakage power of DSP IPs ...

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require ins...

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Col...

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will incl...

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is require...

Power fundamentals. Good knowledge of PTPX. Good knowledge of CLP. Knowledge of design verification, RTL coding, synthesis, and physical design. Protocol knowledge of DDR, CHI, Cache, computer organization, bus protocol. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardw...