11 Vclp Jobs

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5nm, and 16nm. You should possess a strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff. Experience with EDA tools like Genus, Fusion Compiler, PrimeTime, Tempus, and Conformal will be beneficial for this role. Additionally, strong scripting skills in Perl, TCL, and Python for automation and flow development are required. If you meet the above requirements and are excited about this opportunity, click on the Apply option or share your resume with Heena at heena.k@randstad.in.,

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to ratul.chakraborty@modernchipsolutions.com.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC low power convergence and power analysis. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work closely with architecture, RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL and PD team for chip level power estimation, analysis and optimization Work closely with CAD team to come up with new flows and methodologies in the power analyisis and low power domains. PREFERRED SKILLSET: 8+ years of professional experience in the industry in low power and power estimation domains. Hands on experience on industry standard tools especially PTPX, Power Artitst, VCLP and CLP. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexities. Your contribution will be crucial in driving continuous improvement in PPA and turnaround time (TAT) metrics. To excel in this role, you must possess deep knowledge of synthesis, timing closure, power optimization, and constraints management. Your experience with low-power, high-performance design at advanced nodes below 5nm will be valuable. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX is required to effectively carry out your responsibilities. Familiarity with scripting languages such as TCL, Perl, and Python will aid in performing tasks efficiently. A BS or MS in Electrical Engineering or a related field along with 9+ years of relevant experience is necessary to succeed in this position.,

Qualcomm India Private Limited is a leading technology innovator that aims to create a smarter, connected future for all by pushing the boundaries of what's possible. As a Qualcomm Hardware Engineer in the Engineering Group > Hardware Engineering, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. The Low Power CAD Engineer position at Qualcomm involves optimizing power domains and enhancing system-level power modeling using advanced technologies like AI, ML, and 3DIC. Key responsibilities include: - Developing advanced Low Power flows and methodologies for estimation, optimization, and signoff - Architecting AI & ML-driven LP flows to improve efficiency and scalability - Collaborating with SoC and Subsystems teams for seamless deployment of robust LP methodologies - Working with EDA tool providers (Synopsys, Cadence) to support emerging technologies in Automotive, AI/ML, and 3DIC - Integrating Low Power methodologies from RTL to final tape-out stages of chip design - Analyzing power reduction strategies for high-performance computing, AI accelerators, and edge devices - Utilizing expertise in Python and Perl for programming & automation to enhance workflow efficiency - Applying strong knowledge of Unified Power Format (UPF) and hands-on experience with CLP/VCLP tools for Low Power static verification - Implementing power estimation and optimization tools like Synopsys PrimeTime PtPx and Ansys Power Artist - Spearheading improvements in Low Power methodology development and ensuring global deployment - Engaging with EDA vendor R&D teams for tool enhancement and debugging - Evaluating next-generation power tools and leading deployment efforts - Communicating complex power concepts effectively through technical communication and collaboration - Operating in a fast-paced environment, requiring strong communication, planning, and execution skills while collaborating with various teams. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including security measures and confidentiality requirements. Staffing and recruiting agencies are advised not to submit unsolicited applications or resumes through the Qualcomm Careers Site. For further information about this role, please contact Qualcomm Careers directly.,

Looking for Siemens EDA ambassadors: Lead Software Engineer for Product Validation and Customer support for PowerPro If you are passionate about innovations that lead to real progress, and if you are curious about technologies that are yet to be developed, then this opportunity might be for you. Utilize your curiosity, passion, and creativity to enhance the lives of millions of people. Join us and share your unique perspective with us! As a valuable member of the Siemens EDA team, your role will involve contributing to the growth of efficiency and customer satisfaction within Siemens EDA's Power platform. This challenging position aims to support the expansion of Siemens's EDA business in India. You will be a part of the DDCP (Digital Design Creation Platform group), which encompasses renowned industry tools like Tessent, PowerPro, Catapult, and Aprisa. Operating within the DPRS (Devops, Product, Release & Support group) under DDCP, you will be focused on cutting-edge tools like PowerPro. Your responsibilities will revolve around Product Validation, Customer Support, and Release tasks for the PowerPro tool, a commercially available RTL sequential power optimization and power analysis tool. Join our energetic and passionate team driven by synergy and enthusiasm. **Key Responsibilities:** - Collaborate with the Product Validation and Customer Support team to validate and educate on the features of PowerPro. - Validate all features of the tool as an internal end-user, identify and report issues, develop test plans, write test cases, and enhance the product quality and test environment. - Assist in supporting and debugging customer test design methodologies using our products. - Engage in architecture reviews, contribute to defining feature prototypes, understand customer design flow requirements, and propose optimization measures. - Analyze customer-reported bugs, enhance testing procedures, incorporate new designs/flows, respond to customer inquiries using technical expertise, demonstrate products, and provide field application support to customers. - Lead and mentor 1-2 junior team members or interns, guiding them in their day-to-day activities. **Qualifications:** - B.Tech in Electrical/Electronics & Communication Engineering or M.Tech in VLSI/Microelectronics with 3+ years of relevant industry experience. - Profound knowledge of ASIC design flows, digital logic, and RTL/gate-level simulation and verification methodologies. - Proficiency in Verilog, VHDL, and SystemVerilog (SV). - Demonstrated understanding of low-power SoC design concepts, including power intent (UPF) and power-aware design methodologies. - Experience with simulation, synthesis, place & route tools and flows. - Hands-on expertise with industry-standard tools such as Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, and Design Compiler (DC). - Proficiency in scripting languages like Perl and Tcl, with knowledge of Python being advantageous. - Strong problem-solving, debugging skills, and familiarity with RTL/gate-level simulation, emulation, SPEF, and various technology nodes. - Experience in EDA CAD support for RTL design teams is a plus. - Excellent communication skills, adaptable, collaborative, self-driven, and experienced in team leadership. Siemens is a global organization with over 377,000 individuals shaping the future in more than 200 countries. We are committed to equality and welcome applications that represent the diversity of the communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business needs. If you bring curiosity, creativity, and the drive to shape tomorrow, we invite you to join us on this journey. Transform the everyday. Accelerate transformation. Hybrid.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power design. We require UPF expertise as a primary skill, not as a secondary one. It is acceptable to have one back end and one front end with PNR, guided by one consultant. The responsibilities include RTL UPF coding, LP validation, level shifter strategy, and potentially handling UPF within the PNR flows. If the candidate is not familiar with PNR flows, we can fill that gap with a back end UPF person.,

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. Experience with a scripting language such as Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience implementing image/video processing blocks or other multimedia IPs such as Display or ISP Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks Experience in scripting languages, C/C++ programming and software design skills. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and by using different RTL QC tools like Lint, CDC, VCLP. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis. Develop RTL implementations that meet competitive power, performance and area targets. Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA) or silicon bring-up. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture or micro-architecture planning. ,

Greetings from Quest Global Please find the details and kindly send me your Profile . RTL Design 10-15 Years Location : Bangalore/Hyderabad 1. Should have worked on ASIC/SOC projects using 22nm or smaller technology node 2. Expertise in automated RTL Integration using any of the industry standard tool/EDA flow 3. Expertise in SDC and UPF constraints development and checking 4. Expertise in Timing violation debug/fix at netlist level 5. Good knowledge on AHB/AXI/APB/PIPE interface 6. Expertise in Lint, CDC and VCLP, Synthesis, LEC 7. Very Strong in Python and TCL scripting • Nice to have skills: 8. Exposure to PCIe/Ucie 9. Experience in Leading small rtl design team • Location: Bangalore and Hyderabad • Notice period: max 45 days Please forward your updated profile to chakradhar.marupuru@quest-global.com below details Current CTC : Expected CTC: Notice Period : Best Regards Chakradhar M , Email:chakradhar.marupuru@quest-global.com | www.quest-global.com. Assistant Manager Quest Global Whatsapp No : 99869 21214 , Mob: +601 736 16576 Quest Global, Penang – Mayang. Unit 1.13-17 GBS@Mayang , Lengkok Mayang Pasir, Bayan Baru 11950,Penang, Malaysia