31 Vclp Jobs

Role: Lead /Senior RTL Engineer Experience: 8 to 12 Years Location: Chennai Job Description: Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.

Role: Lead /Senior RTL Engineer Experience: 8 to 12 Years Location: Hyderabad Job Description: Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDD...

As a Manager / Senior Role Physical Design Engineer at Radiant Semiconductors in Hyderabad, you will be responsible for the following key responsibilities: - Execute IP/Block level PnR activities from Netlist to GDS-II - Demonstrate proficiency in all PnR activities including Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Implement all Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handle signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Utilize knowledge of high performance and low power implementation methods - Showcase expertise in tools like ICC2/Fusion Co...

Role: RTL Engineer. Experience: 4 to 12 Years Location: Bangalore Job Description: Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.

Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience. Deatiled JD is below as mentioned... Candidates with PnR 8+ experience IP/Block level PnR activities from Netlist to GDS-II. Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV. Knowledge of industry stanrd E tools (Synops, Cadence, Mentor) Worked on DSM technologies, tsmc 5nm and below experience preferred. Knowledge of scripting skills. Minimum Experience : 8+

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

About the team: You will join a dynamic, global team of experts dedicated to advancing the state-of-the-art in high-performance cores and IP implementation. The team is at the forefront of developing innovative methodologies and leveraging Synopsys industry-leading tools to solve the most critical design challenges in semiconductor technology. Job Description Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes. Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI. Drive flow development and optimization to improve design quality and p...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), defining design constraints (SDC) and Low-power intent (UPF). Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience in design and development of audio blocks or Mobile Industry Processor Interf...

As an ASIC RTL Design Lead at our Hyderabad location, you will be responsible for the following: - Hands-on experience in RTL Design using Verilog - Expertise in SoC and Subsystem integration, including peripherals like PCIE, Ethernet, and USB Integration - Front-end flow environment bringup - Proficiency in flows such as Lint, CDC, Synthesis, Formality, VCLP - Knowledge of TCL or Perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff Qualifications required for this role: - Total Years of Experience: 10+ years If you possess the skills mentioned above and are ready to join us immediately, please share your profile with us at ratul.chakraborty@modernchipsolut...

Job Requirements We are looking for a highly experienced and technically strong Senior Lead Physical Design Engineer with 12+ years of hands-on expertise on complex block or subsystem-level physical design on complete RTL to GDSII activities and must be passionate about driving power and area efficiency, methodology innovation, and signoff convergence. Key Responsibilities: Drive RTL-to-GDSII activities including synthesis, floor planning, power planning, , placement, CTS, routing, and signoff tasks. Experience on multi-voltage and multi-power domain designs using UPF and low power verification (VCLP/CLP) Perform dynamic and leakage power analysis (using PTPX) and optimization across design ...

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Working with SOC Architects to understand low power architecture Identifying the stages where level sh...

Were Hiring – RTL Design / Low-Power Verification Engineer (UPF / VCLP Expert) Are you passionate about RTL Design and Low-Power SoC Verification ? Join ACL Digital and be part of an innovative semiconductor design team driving next-gen chip solutions! Location: Bangalore Experience: 5+ Years Notice Period: Immediate to 30 Days What You’ll Do Define, develop, and validate Unified Power Format (UPF) for multi-voltage, power-gated SoC/ASIC designs. Perform power intent verification using Synopsys VC LP / PrimeTime PX / Cadence CLP . Analyze and close VCLP warnings and errors — isolation, retention, and level shifter strategies. Collaborate with RTL & PD teams to ensure correct low-power cell i...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will have the opportunity to plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Developing advanced Low Power flows and methodologies for estimation, optimization, and signoff - Architecting AI & ML-driven LP flows to improve efficiency and design scalability - Collaborating with SoC and Subsystems teams for seamless deployment of robust LP methodologies - Working wi...

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. - Developing innovative methodo...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to he...

3+ years experience Synthesis and STA Engineers Experience with power analysis using power artist and PTPX Experience with sign off static timing analysis, static low power checks, logic equivalency checks Static timing analysis and ECO flows and achieve timing closure

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5n...

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will h...

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexiti...

Qualcomm India Private Limited is a leading technology innovator that aims to create a smarter, connected future for all by pushing the boundaries of what's possible. As a Qualcomm Hardware Engineer in the Engineering Group > Hardware Engineering, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. The Low Power CAD Engineer position at Qualco...