MTS Silicon Design Engineer

5 - 10 years

40 - 45 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
  • Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
  • Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
  • Develop and adopt FEINT design and verification infrastructure, methodology and tools

Preferred experience:

  • BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years
  • Proven understanding of RTL design, synthesis, and ECO principles
  • Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc.
  • Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
  • Excellent skills with Unix/Linux environment
  • Familiar with RTL coding techniques for competitive PPA-measured QoR
  • Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
  • Good understanding of gate level circuit design and physical level design concept and methodology
  • Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments
  • Excellent communication skills (both written and oral)
  • Self motivated, and committed to achievement

Academic credentials:

  • Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or possibly a related field
  • Masters Degree preferred

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