Principle RTL Engineer

Silicon Image India Research Development

12 - 17 years

8 - 12 Lacs

pune

Posted:1 day ago| Platform:

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Skills Required

c++ simulation xilinx vhdl fpga modelsim debugging tcl protocols system verilog arm fpgas communication skills architecture synthesis sta python c eda software testing altera system design rtl verilog hdl microcontroller system hardware design pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

Lead the design and development of FPGA debug engine in Lattice EDA suite.
Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features.
As a principal RTL Engineer, you will work closely with marketing requirements and generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams and ensure that implementations match design intent.
Mentor and guide junior RTL & UI engineers working on FPGA debug IP, fostering a culture of continuous improvement and innovation.
Maintain high standards of architecture, implementation quality, performance, and reliability.
Improve development methodologies and processes.

Qualifications

Master s in Electrical engineering/Computer engineering or related field with 12+ years of experience in RTL System Design and EDA experience.
Strong communication skills.
Expertise in HDL languages (Verilog/System-Verilog and VHDL).
At least 15 years of Hardware design experience.
At least 10 years of Hardware Design experience using FPGAs.
At least 5 years on FPGA debugging methodologies.
Proficiency in synthesis tools.
Proficiency in simulation tools from leading EDA vendors.
Proficiency in testbench/test-vector creation.
Proficiency in C/C++ , TCL, Python languages.
Proficiency in protocols such as Serdes interface, Ethernet, PCIe or Memory DDR is required.

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