1850 System Verilog Jobs - Page 5

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market. Hold a Bachelor or masters degree in electrical or computer engineering Have a minimum 2 ye...

* Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. * Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. * Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. * Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. * Develop verification test plan for both functional and pe...

We are seeking highly motivated individuals with a BS, MS, Btech or Mtech degree in Electronics engineering to be part of the EDA team. Join a great team of engineering professionals who are involved in development, validation & release of IBM CAD tools & methodologies used in designing IBM P & Z microprocessor systems along with system ASICS. In this role, you are expected to enable different flavours of the backend design( RTL-GDS ) flows and assess the quality of tools. Develop automation scripts to aid tool in data analysis/visualization. You are required to have excellent debugging skills and have good understanding of RTL-GDS implementation flow for 5nm and below technologies. We are s...

As a Senior Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performanc...

Responsibilities: * Collaborate with cross-functional teams on SOC verification * Develop testbenches using System Verilog and Verilog * Ensure compliance with industry standards and customer requirements

People-driven culture This is for an experienced systems engineer (SE) position in the airplane systems engineering organization in the Boeing Commercial Airplanes (BCA) BU. As a member of this team, you will be responsible for System development of aircraft network system, aircraft interface device, computing device, electrical sub-systems, development Assurance (ARP4754A), Validation & Verification and traceability of requirements. Also, you will be responsible for Systems design, system level requirements development, decomposing requirements, testing, and supports FAA certification documents. Position Responsibilities: Demonstrate excellence in development of high-integrity aircraft netw...

Role Overview: You will be responsible for independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own tasks related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client. Additionally, you will be expected to automate design tasks flows, write scri...

As a Senior SOC Verification Lead/Manager at Modern Chip Solutions, you will be responsible for ASIC Verification with a focus on SOC verification. Your key responsibilities will include: - Utilizing System Verilog and Verilog for verification tasks - Implementing UVM methodology for verification purposes - Working with various protocols such as DDR, Ethernet, and PCIe To qualify for this role, you should have: - Minimum 10+ years of experience in ASIC verification - Strong expertise in System Verilog, Verilog, and UVM - Familiarity with protocols like DDR, Ethernet, and PCIe would be advantageous For further details or to express your interest in this position, please contact Anand Arumugam...

As a Verification Engineer at Synopsys, you play a crucial role in ensuring the highest standards of quality in complex system designs. With over a decade of experience in IP verification, you possess a deep understanding of verification methodologies and hardware design intricacies. Your expertise in designing self-checking test benches, developing verification components, implementing functional coverage and assertions using System Verilog, and debugging simulation failures makes you a valuable asset to any team. **Key Responsibilities:** - Designing and implementing self-checking test benches using modern verification techniques. - Developing verification components such as bus functional...

Role Overview: You will be responsible for ASIC RTL design with 10+ years of experience and proficiency in Verilog/System Verilog. Your role will involve working with multiple clock and power domains, integrating and validating various MIPI cores, debugging, and implementing CSI/DSI controllers. Additionally, you will be creating micro-architecture specifications, reviewing vendor IP integration guidelines, running integrity check tools, and participating in design verification and physical implementation processes. Key Responsibilities: - Possess 10+ years of ASIC RTL Design experience and proficiency in Verilog/System Verilog - Work with multiple clock and power domains - Integrate and val...

As an ASIC Intern at NVIDIA, you will be part of our world-class hardware teams, working on cutting-edge designs that power GPUs, CPUs, SoCs, and VLSI systems for next-generation computing platforms. Depending on your interests and skills, you could contribute to architecture, design, or verification across domains such as high-performance graphics, AI processors, VLSI design, and advanced CPU and SoC technologies. **Key Responsibilities:** - C++/System Verilog modelling, test development, and RTL design/debug - Architecture, micro-architecture, and performance verification - Developing verification environments (e.g., UVM), test plans, and reusable components - Scripting and automation with...

As a Lead Product Engineer at Cadence, you will play a crucial role in driving the development of products and technologies, with a significant responsibility for their success. Your expertise in the UCIe domain of Verification IP family, both protocol and product-wise, will be essential in accelerating the adoption of the VIP portfolio at Cadence's top tier customers through pre-sales technical activities. Your main responsibilities will include understanding customer design and verification flows, providing training, developing collaterals, and translating high-level requirements into technical specifications to meet customer needs. Collaboration with R&D, Marketing, and support teams will...

Role : Design Verification Work Location : Preferred Pune WFO, If candidate is found to be excellent Noida or Bangalore Remote options are open Years of Experience : 4+ Years Education Qualification : MS (or higher) in EE/EC/ECC Engineering Skills Must have excellent knowledge of computer architecture and design verification fundamentals. Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies. Experience in developing complex test bench in System Verilog using OVM/ UVM methodology. Hands-on experience in AMBA protocol, PCIe MAC/ USB /MAC/ Bluetooth MAC/ Wifi 802.11 MAC layer protocol. Experience in Low Power Simulation/UPF setup, d...

You will be working as a DV Engineer at Qualcomm India Private Limited with a focus on SOC design verification. Your main responsibility will be to understand the internal requirements and complexities of highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. Your early involvement in DV will also require you to participate in architecture/product definition through early involvement in the product life-cycle. **Key Responsibilities:** - Define verification architecture, develop test plans and build verification environment -...

As a Verification Engineering Manager, you will lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. You will ensure the definition and implementation of test and verification plans, collaborating with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements. Monitoring and analyzing coverage reports will be crucial to ensure thorough verification, and you will be responsible for identifying and resolving verification issues and bugs to ensure timely project delivery. Continuously improving verification processes, methodologies, and tools will also be a key part of your role. Managing p...

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

Job Description Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify desi...

Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cas...

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco''s silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integr...

Software Engineer- C Programming,Networking platform development, PHY drivers, SERDES, SFP- 4-8 Years Meet the Team The Enterprise Switching organization delivers top-tier products, with the Catalyst Cat9000 series leading in core, aggregation, and access switching for security, IoT, and Cloud. These switches are critical for SD-Access, Cisco''s intent-based networking architecture, offering the bandwidth, speed, and scale needed for hybrid work environments. They improve security with PoE power and AI/ML for zero-trust security and provide outstanding network experiences both on-premises and in the cloud through Cisco DNA Center or the Meraki Dashboard. The new Catalyst 9000X models offer f...

Infra team supports all hardware and engineering development divisions for general cross-divisional development infrastructure. This group is responsible for a large breadth of existing and emerging tools supporting Engineering at NVIDIA. What You ll Be Doing C++/System Verilog modelling, test development, and RTL design/debug Architecture, micro-architecture, and performance verification Developing verification environments (e.g., UVM), test plans, and reusable components Scripting and automation with Python/Perl Performance evaluation, power estimation, and low-power verification Collaboration with architects, designers, and post-silicon teams What We Need to See Strong academic background...

We are seeking a visionary Staff Engineer as part of System Validation Infra to join our team in Bengaluru, India. In this pivotal role, you will lead the technical direction of our engineering efforts, drive innovation, and mentor our talented team of engineers. As a Staff Engineer, you will be at the forefront of designing and implementing cutting-edge solutions and monitoring infra tools and systems deployment that shape the future of our products. Working on high-performance Infra software that meet business requirements and industry standards Working on the development of technical strategies and roadmaps to guide long-term engineering initiatives Collaborate with cross-functional teams...

Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit

About the Role: We are seeking an experienced Design Verification Engineer with 5 to 10 years of hands-on experience in verifying complex digital designs, particularly in IP cores, SoCs, and PCIe protocols. The ideal candidate will have deep expertise in developing and executing verification plans, writing testbenches, and automating verification environments to ensure high-quality silicon delivery. Key Responsibilities: Develop and implement comprehensive verification plans and strategies for IP, SoC, and PCIe blocks. Create and maintain advanced verification environments using SystemVerilog, UVM (Universal Verification Methodology), and other relevant methodologies. Write and debug directe...

Key Responsibilities: Perform gate-level simulations (GLS) for ASIC/SOC designs post-synthesis and post-layout. Validate timing, power-up behavior, clock gating, and low-power modes (with UPF/CPF ). Develop and execute GLS test plans including functional, scan, and ATPG pattern verification. Work closely with RTL design, DFT, STA, and backend teams for issue resolution. Debug timing-related issues in post-layout netlist simulations . Ensure zero-delay and SDF-annotated simulation coverage. Requirements: Strong experience in GLS verification at the netlist level with SDF annotation. Solid understanding of timing closure , STA concepts, and simulation tools. Proficient in SystemVerilog , scrip...