1277 System Verilog Jobs - Page 3

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab/NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up.

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab /NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up. Skills : - Staff Design Engineer, RTL Design, System Verilog, ASIC, FPGA, DSP, Signal Processing, AMBA, Micro-Architecture, SoC, Low-Power Design, Verification, Matlab, NumPy, C, C++, LPDDR, SerDes, MIPI, Ethernet, FPGA Validation, Post-Silicon, Diagnostics Firmware

Emulation Engineer with Zebu experience- digital systems RTL code for IP, sub-systems, and SoCs. hardware description languages (HDLs) such as Verilog or system Verilog Experience in building emulation model builds Email id - ta6@nippondata.com

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and enhance test suites for improved quality. Work on assertion-based and formal verification techniques where applicable. Contribute to automation and scripting to streamline verification flows.

Education: Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech) Roles & Responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects Required Skills and Experience Curious, demanding and rigorous. Mastering object oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog SystemC hardware verification languages Knowledge of Constraint-Random Coverage-Driven verification environments development in SystemVerilog C ++ (drivers monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp SVA) Knowledge of simulation tools and coverage database visualization tools Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. Our Offering: Competitive salary package Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave. Benefit Plans (Insurance) Medical & Life & Accidental & EDLI

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities MTS (Development and Validation) Responsible for deep understanding, architecting and implementing of complex System Validations frameworks involving custom devices driver for hardware and firmware solutions like Storage Devices like SSD Responsible for thinking complex field scenarios and implementing algorithms to simulate them. Skills Must have 7-15 yrs exp Experience and Mandatory knowledge in PCIe, NVME/Storage devices and drivers. Experience in terms of device drivers of PCI devices like ethernet devices. Experience in C/C++ programming Experience in some System-Level Validation frameworks along with automation where we are validating different hardware and firmware components from host on top of device drivers. Past experience of grey box testing software Experience with development of complex software code base , debugging and fixing the issues Experience in Linux Operating system concepts and Qemu Experience with Multi-threaded software development in Linux environment Knowledge of core computer science concepts such as object-oriented design, algorithm design, data structures, problem solving, and complexity analysis Experience in Software programming for FPGAs is an advantage Nice to have Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Location - pune,mumbai,chennai,banagalore

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 6+ years of experience. Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: RTL coding.Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

As a Lead Product Engineer at Cadence, you will drive the development of cutting-edge products and technologies in the UCIe domain of Verification IP family. You will play a pivotal role in accelerating the VIP portfolio adoption at Cadence's top tier customers by providing expert support in pre-sales technical activities. Your responsibilities will include translating high-level requirements from customers into technical specifications, developing product definitions that align with customer needs, and ensuring successful product knowledge transfer across field engineers and customers. To excel in this role, you must have a solid background with at least 5 to 8 years of experience in Verification and Design. Working knowledge of the UCIe domain and functional verification, experience in developing verification environments using System Verilog, and familiarity with the UVM methodology are essential. Strong problem-solving and debugging skills are a must, as you will be required to analyze complex situations and data to drive product success. Your qualifications should include a BE/BTech/ME/MS/MTech degree in Electrical, Electronics, Computer Science, or equivalent field. In addition to technical expertise, you must possess excellent written, verbal, and presentation skills to establish effective working relationships with customers and internal stakeholders. Your ability to think creatively, work collaboratively across functions and geographies, and maintain integrity while striving for excellence will be key to your success in this role. Join us at Cadence, where you will have the opportunity to work with a diverse team of passionate and talented individuals dedicated to making a positive impact on the world of technology. Be part of our innovative culture that values creativity, collaboration, and continuous learning. We are committed to supporting your physical and mental well-being, career development, and success, and we celebrate achievements that recognize the unique needs of our employees. At Cadence, we are solving challenges that others can't. Come be a part of our team and help us make a difference.,

At QpiAI, we are leading the effort to discover optimal AI and Quantum systems in Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. QpiAI is building a full stack Enterprise Quantum Computers. QpiAI Quantum hardware team is responsible for designing and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are seeking a skilled and motivated Hardware Verification Engineer to join our Hardware team. Together, we will build the next generation of life changing custom hardware for Quantum computers! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be. In this position, you will be creating models and test plans for verifying functionality and performance of inhouse chip designs. You will understand the design, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Requirements: - BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science or related degree required, advanced degrees (MS, PhD) preferred - 3+ years of relevant work experience - Proficiency in verification languages (System Verilog or equivalent) and methodologies (UVM or equivalent) - Experience with verification tools such as VCS and Verdi - Good debugging and problem-solving skills Join us at QpiAI and be part of a team that is shaping the future of Quantum computing hardware!,

As a Lead Product Engineer at Cadence, you will be driving the development of cutting-edge products and technologies in the UCIe domain of Verification IP family. With a primary responsibility for the success of the product/technology, you will play a crucial role in accelerating the VIP portfolio adoption at our top-tier customers by providing expert support in pre-sales technical activities. Your role will involve leveraging your strong verification expertise to understand customer design and verification flows, translating high-level requirements into technical specifications, and driving product definitions that align with customer needs. In this role, you will be expected to be an expert in UCIe domain and protocol, with working knowledge and experience in developing verification environments using System Verilog. Your experience with the UVM methodology and problem-solving skills will be essential in solving complex problems and ensuring the alignment of all dimensions of the product. Collaboration with cross-functional teams such as R&D, Marketing, and support will be crucial to ensure the success of the product. The role of Lead Product Engineer requires approximately 20% travel on average, offering you the opportunity to work with a diverse team of passionate and talented individuals. Cadence's employee-friendly policies focus on your physical and mental well-being, career development, learning opportunities, and celebrating success, ensuring a supportive and collaborative work environment that promotes innovation and creativity. To qualify for this role, you should have at least 5 to 8 years of experience in Verification and Design, along with a BE/BTech/ME/MS/MTech degree in Electrical/Electronics/Computer Science or equivalent. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. Your willingness to explore unconventional solutions, work effectively across functions and geographies, and strive for excellence while operating with integrity will be key to your success in this role. Join us at Cadence and be part of a team that is dedicated to making an impact in the world of technology. Your contributions will help us solve challenges that others can't, driving innovation and success for our customers, communities, and each other every day.,

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. This entails supporting all leading DDR memory protocols including DDR4/LPDDR4. You will collaborate on working with the existing RTL, incorporating new features, ensuring customer configurations are clean during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. To qualify for this role, you should hold a BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI and possess significant experience as a design and verification engineer, with a focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, while experience with System Verilog and familiarity with UVM based environment usage/debugging are also required. AXI3/4 experience is desired, and prior exposure to DDR Memory controller and protocol is highly desirable. Having prior experience in RTL design and implementation of complex protocols, as well as in IP development teams, would be advantageous. Join us at Cadence, where we hire and develop leaders and innovators who strive to make a significant impact on the world of technology. Together, let's tackle challenges that others cannot solve.,

You have a unique opportunity to join Astera Labs, a global leader specializing in purpose-built connectivity solutions that unleash the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform seamlessly integrates PCIe, CXL, and Ethernet semiconductor-based solutions along with the COSMOS software suite, offering a software-defined architecture that is not only scalable but also customizable. Building on strong relationships with hyperscalers and the data center ecosystem, we are at the forefront of innovation, delivering flexible and interoperable products that are transforming modern data-driven applications. Explore more about our groundbreaking work at www.asteralabs.com. As a candidate, you should possess a Bachelor's degree in electrical engineering (EE), with a preference for a Master's or Ph.D. in EE, accompanied by a background in Math or Computer Science. You should have a minimum of 8 years of experience in formal verification or 7 years in traditional design verification (DV). A strong work ethic, adept at managing multiple tasks in a dynamic environment, is essential. Your ability to plan for customer meetings, work independently, and exhibit an entrepreneurial mindset with a customer-centric approach are key attributes. Proficiency in cross-functional collaboration is also vital for this role. Your responsibilities will include developing detailed formal verification (FV) test plans based on design specifications and collaborating with design teams to enhance micro-architecture specifications. You will identify crucial logic components and micro-architectural properties to ensure design correctness. Implementing formal verification models, abstractions, and assertions, utilizing assertion-based model checking to detect corner-case bugs will be part of your role. You will apply complexity reduction techniques, develop scripts for enhanced productivity, and assist in implementing assertions and formal verification testbenches for RTL at unit/block levels. Your involvement in design reviews and collaboration with design teams to optimize design quality based on formal analysis feedback will be crucial. Proficiency in System Verilog/Verilog and scripting abilities with Python or Perl are required. Preferred candidates will have hands-on experience with formal verification tools like Synopsys VCFormal and Cadence JasperGold, along with familiarity in automating formal verification workflows within a CI/CD environment. At Astera Labs, we value diversity and inclusivity, believing that creativity and innovation thrive in a team with varied ideas, backgrounds, and experiences. We actively encourage individuals with diverse backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and persons with disabilities, to apply and be part of our dynamic team.,

As a member of our team, you will have the opportunity to work on cutting-edge Application-specific integrated circuit (ASIC) projects that are at the forefront of technology. Your role will involve collaborating with various teams within the organization, such as architecture, verification, power and performance, and physical design, to develop high-quality designs for next-generation data center accelerators. You will be responsible for defining and implementing physical design methodologies, taking ownership of specific design partitions or top-level designs, and ensuring the closure of timing and power consumption aspects of the design. Your contributions to design methodology, libraries, and code reviews will be crucial in delivering successful projects. In this role, you will also play a key part in defining physical design-related rule sets for functional design engineers. Your expertise in advanced design principles, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs, will be essential in shaping the future of our hardware experiences. We are looking for individuals with a Bachelor's degree in Electrical Engineering or equivalent practical experience, along with at least 4 years of experience in advanced design. A Master's degree in Electrical Engineering or a related field is preferred. Experience with System Verilog, scripting with TCL, and VLSI design in SoC will be advantageous for this role. Join us in developing custom silicon solutions that drive innovation and power Google's direct-to-consumer products. Your contributions will play a vital role in delivering unparalleled performance, efficiency, and integration, shaping the next generation of hardware experiences loved by millions worldwide.,

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. You have the opportunity to join the Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, two industry leaders have united to create an optical networking powerhouse, combining cutting-edge technology with proven leadership to redefine the future of connectivity. As an FPGA Verification engineer, you will play a crucial role in designing verification plans, developing environment/testbenches, creating test scenarios for running simulations, conducting coverage analysis, and providing lab support during board bring up to ensure the quality of Infinera products. You should possess the ability to handle projects independently and demonstrate a strong drive for finding solutions. Your responsibilities will include developing and executing verification plans for high-complexity DWDM systems used in LH/ULH optical network applications, designing and implementing simulation environments and testbenches, running test scenarios to ensure comprehensive design coverage, performing coverage analysis, collaborating with cross-functional R&D teams, providing lab support during board bring-up, and managing verification projects independently with a proactive approach. Key skills and experience required for this role include 12-16 years of experience in developing System Verilog UVM based test environments, HVL coding skills for Verification, familiarity with UVM verification methodologies, knowledge of HDLs such as Verilog and scripting languages like perl, conversance with technologies like Ethernet, PCIe, I2C, SPI, structured analytical and troubleshooting skills, good communication skills, and a self-driven and innovative mindset. Nokia is committed to innovation and technology leadership across mobile, fixed, and cloud networks. Joining Nokia will provide continuous learning opportunities, well-being programs, opportunities to join employee resource groups, mentoring programs, and the chance to work in highly diverse teams with an inclusive culture. Nokia is an equal opportunity employer committed to creating a culture of inclusion where everyone feels respected, included, and empowered to succeed.,

You will be responsible for the Tools and Infrastructure Platforms for the engineering team at Ethernovia. This responsibility includes developing software for Ethernovia's Evaluation platforms that are used to debug, test, and demonstrate the company's networking devices. This software includes BSP (Board Support Packages), drivers for onboard devices, middleware software. Our products and hence tool infrastructure is quite data intensive and we are looking for candidates who are able to create tools for handling large volume of test data output and help visualize this data in command line and graphic tools. Technical Qualifications Bachelors or Master's degree in Computer Science/Software or related field. Work Experience: 3 years for Mid-level and 7 years for Senior Level position. Strong understanding of Software Development lifecycle including Architecture, Implementation and Testing fundamentals. Proficient in C/C++ Programming Language. Experience in Python is a plus. Experience with BSP (Board Support Packages) preferably Linux systems like Beaglebone or Raspberry Pi. Device drivers, preferably for devices on hardware buses like I2C, SPI and Ethernet. Good understanding of Operating systems preferably Embedded Linux. Experience with integration and testing of open-source middleware, libraries, and drivers. Hands on Experience with Hardware and embedded processors. Nice to Have Experience with GNU or similar compiler, debugging suite. Embedded programming, preferably with communication devices and hardware buses like I2C, SPI, Ethernet, USB. Code Version Control and Review tools/processes like Perforce/Git, Swarm. Automation and DevOps tools like Jenkins. ARM family of processors or similar embedded processors. Performance testing of communication devices. GRPC, Protobuf or similar Remote Procedure Call (RPC) software. Boot code like uboot or similar. Experience in Verification/validation experience including HW languages (System Verilog, Verilog, UVM) is a big plus. Experience in SystemC and transaction-level modelling (TLM). Soft Skills Self-motivated and able to work effectively both independently and in a team. Excellent communication/documentation skills. Attention to details. What you'll get in return: Pre IPO stock options Cutting edge technology World class team Competitive base salary Flexible hours Medical, dental and vision insurance for employees Flexible vacation time to promote a healthy work-life balance,

As a FPGA & Board Design Engineer with 2 to 5 years of experience, you will be responsible for developing new hardware designs. This includes system design, CPLD/FPGA or processor design, and board-level analog/digital circuit design for embedded systems/boards. Your primary task will be to create detailed specifications based on requirements and implement hardware designs accordingly. You will work closely with the CAD team for layout review and feedback, perform simulation activities, and develop test benches to complete the verification of FPGA designs. Additionally, you will be involved in proto H/W bring-up with support from firmware engineers. To qualify for this role, you should hold a B.Tech. or M.Tech. in EE with at least 2+ years of FPGA experience, including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL, and System Verilog is required, along with experience in tools such as Synopsys Synplify, Xilinx Vivado, and ISE. Hands-on experience with FPGA debug methodologies, schematic capture tools, lab debug equipment, and scripting skills in Perl/Python are essential. Knowledge of high-speed interfaces like PCIe, Ethernet, and DDR3/4, as well as low-speed interfaces including SPI, IIC, and UART, is expected. Experience in test bench design and implementation, designing with Altera and Xilinx FPGAs, and strong attention to detail are also necessary. Good interpersonal skills and excellent written and verbal communication skills are a bonus for this role.,

Qualcomm India Private Limited is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. As a GPU Functional Verification Engineer at Qualcomm, you will be responsible for developing a deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces. Your tasks will include strategizing, brainstorming, and proposing a DV environment, developing a test bench, owning a test plan, debugging all RTL artefacts, and achieving all signoff matrices. You will engage with EDA vendors to explore new and innovative DV methodologies to push the limits of sign off quality. Collaboration with worldwide architecture, design, and systems teams will be essential to achieve all project goals. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Desired Skills: - Strong knowledge of UVM based System Verilog TB - Knowledge of GPU pipeline design is a plus - Proficiency with formal tools - Working knowledge of Property based FV is a plus - Strong communication skills (both written and verbal) - Ability to learn, improve, and deliver Experience: - Minimum 3 years of Design verification experience - Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education Requirements: - BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities Selected candidates will join the GPU HW team at Qualcomm, passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. The pre-Si verification team in Bangalore is heavily involved in various activities including UVM/SV based constrained random test bench for functional verification, Subsystem level TB for complete GPU workload analysis and compliance, Emulation platforms for performance analysis, Formal tools for bug identification, Power Aware & Gate level simulations, and Perl/Python scripts for automation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities to participate in the hiring process. The company expects its employees to abide by all applicable policies and procedures, including those related to the protection of confidential information. Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through Qualcomm's Careers Site. For more information about this role, please contact Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking VLSI Digital Design Engineers with 2 to 20 years of experience to join the Bangalore WLAN PHY (Baseband) team. The team is responsible for leading IP development for the latest WiFi standards. As part of the WLAN PHY team, you will work with a group of highly passionate domain experts, specializing in taking WLAN PHY designs from concept to silicon independently. The team focuses on delivering end-to-end Tx/Rx DSP chains, from antenna samples post ADC to raw bits for upper layers and vice versa, emphasizing on practical high-speed wireless communication systems and innovative solutions to address challenges. As a Digital Design Engineer, you will be involved in working on signal processing functions like filters, matrix transformations, channel estimation, equalization, decoders/encoders, demodulators, FFT, and more on a daily basis. You will contribute to developing and enhancing signal processing algorithms to meet new requirements. If you are passionate about your work and interested in contributing to the WiFi revolution, this opportunity is for you. Qualcomm aims to be a global leader in WiFi chip solutions, and the WLAN PHY team in Bangalore plays a crucial role in achieving this vision. The ideal candidate should have 1 to 3 years of experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding, familiarity with RTL QA flows like PLDRC, CDC, and optionally CLP, is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading or managing junior team members and a track record of successfully taking IP designs from requirements to silicon are advantageous. While not mandatory, experience in developing IPs for wireless technologies or past HLS experience would be beneficial. Key skills required for this role include proficiency in Verilog RTL coding, micro-architecture, CDC checks, PLDRC, Timing constraints, Python/Perl, and experience in designing/debugging complex data-path/control-path IPs. Good communication, analytical, and leadership skills are essential. Additional skills such as System Verilog, Visio, knowledge of signal processing concepts/algorithms, Wi-Fi standards, and HLS experience are considered a plus. Qualcomm is looking for candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related fields with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience in the same field. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm via the provided contact information.,

As a Wireless Modem HW Model Developer at QCT's Bangalore Wireless R&D HW team, you will have the opportunity to work on Qualcomm's cutting-edge chipsets in modem WWAN IPs. Your primary responsibilities will include contributing to the development of flagship modem core IP for 5G (NR) and 4G (LTE) technologies. You will play a key role in defining and implementing next-generation multi-mode 5G modems. Your daily tasks will involve developing and verifying HW models of modem core IP using C++/SystemC platform. These models serve as the golden reference for RTL verification and pre-Silicon FW development, thereby aiding in virtual prototyping. To excel in this role, you must possess a strong command of C++ and familiarity with SystemC, System Verilog, and/or Matlab. Additionally, you should be adept at understanding HW micro-architecture and modeling abstraction. Ideal candidates will have a working knowledge of the physical layer of wireless technologies such as NR, LTE, WLAN, and Bluetooth. Expertise in digital signal processing and experience in HW modeling, RTL design/verification of IP are highly valued. Those with a background in software/firmware related to wireless IP are encouraged to apply. Moreover, candidates with a solid technical foundation in non-wireless DSP-based HW IPs, encompassing skills in design, verification, and modeling, will also be considered for this role. If you are passionate about innovation and possess the technical acumen to drive advancements in wireless modem HW modeling, we encourage you to join our dynamic team at QCT's Bangalore Wireless R&D HW division.,

We are looking for a highly skilled and motivated Firmware Development Engineer with over 6 years of experience in embedded systems development and testing. As a Mid-Level Firmware Engineer, your responsibilities will include writing C test cases on A78 core with device driver for low/high-speed interfaces. You should have expertise in Zephyr OS or ARM, along with proficient C programming skills and the ability to debug complex firmware issues. Your role will involve working with firmware testing platforms such as emulation and post Si, as well as participating in board, processor, or ASIC bring-up. You should have a proven track record of methodically identifying and resolving complex failure mechanisms at the IP, subsystem, and system levels. Knowledge of firmware algorithms related to Host protocols like SCSI, SATA, eMMC, USB, PCIe, SPI, DDR, NVMe will be advantageous. Additionally, familiarity with security protocols is a plus. Experience in hardware/software interfaces and debugging advanced issues in CPU and firmware using JTAG, source code debuggers, and other tools is essential. Proficiency in source control systems like git/gerrit and working knowledge of Python, C++, UVM, System Verilog, and Verilog is highly desirable. You should have a solid understanding of the firmware development cycle, integration, and verification/validation for both pre-si and post-si SoC designs. Your responsibilities will also include software development and testing, designing complex multithreaded Performant SW, creating SW API interfaces, and programming in C/C++. Experience with multi-threaded software development in a Linux environment, as well as familiarity with Embedded IP subsystems (e.g., Ethernet, PCIe, SPI, I2C, USB, GPIO, Memory architectures, DDR, SDRAM, DMA) is required. Knowledge of software development for x86 platforms, low-level driver development, register interface programming, algorithms, data structures, and bootloaders/Uboot is essential. Strong debugging skills using JTAG debuggers at the device and board level, along with experience in software programming for FPGAs, will be advantageous. Proficiency in scripting languages such as Perl, Python, or TCL is a plus. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required for this position. If you possess excellent verbal communication skills and meet the above qualifications, we encourage you to apply for this exciting opportunity in Firmware Development Engineering.,

As a SOC Verification Engineer with 2-8 years of experience, you will be responsible for verifying complex System on Chip (SOC) designs. You should have a strong proficiency in System Verilog and hands-on experience in Verilog and System Verilog. It is essential to have a minimum of 2 years of experience specifically in SOC Verification. Expertise in C/Assembly languages is also required for this role. Your role will be based in Delhi/NCR, where you will collaborate with a team of professionals to ensure the successful verification of SOC designs. As a self-motivated individual, you will actively contribute to the verification process and work effectively within a team environment. Excellent communication skills are crucial for this position as you will be required to interact with team members and other stakeholders regularly. Being a good team player is another key requirement for this role, as you will be working closely with colleagues to achieve common verification goals. If you are passionate about SOC Verification and possess the necessary skills and experience, we encourage you to apply for this exciting opportunity. Join our team and be a part of cutting-edge SOC design verification projects.,