RTL Micro-Architecture Design Engineer

You have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include: - Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property - Engaging with other architects within the IP level to drive the Micro-Architectural definition - Delivering quality micro-architectural level documentation - Producing quality RTL on schedule by meeting PPA goals - Being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks - Collaborating with the verification team to ensure implementation meets architectural intent - Running quality checks such as Lint, CDC, and Constraint development hands-on - Debugging designs in simulation environments - Having a deep understanding of fundamental concepts of digital design Preferred Skills: - Strong Verilog/System Verilog RTL coding skills - Experience with DRAM Memory Controller design - Knowledge of DRAM standard (DDR4/5) memory - Interface/Protocol experience required - AHB/AXI, Processor local bus, Flash, SPI, UART, etc. - Experience with Xilinx/Intel FPGA Tool flow - Knowledge of PCIe/PIPE - Knowledge of projects with (Microblaze, ARM cores, etc.) - Appreciation for CXL Protocol Qualifications: - Masters degree or Bachelors degree in Electronics or Electrical Engineering - 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.,