RTL Micro-Architecture Design Engineer DRAM Controller Samsung Electronics

5.0 - 14.0 years

0 Lacs

karnataka

On-site

As a VLSI RTL IP or Subsystem designer with 5 to 14 years of experience, you will be responsible for designing and developing CXL and DRAM controller (DDR4/5) based intellectual property. Your role will involve engaging with other architects within the IP level to drive Micro-Architectural definition and delivering quality micro-architectural level documentation. You will need to produce quality RTL on schedule by meeting PPA goals and be accountable for logic design/RTL coding, RTL integration, and timing closure of blocks. Collaboration with the verification team will be essential to ensure implementation meets architectural intent. Your hands-on experience in running quality checks such a...

Posted 2 weeks ago

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RTL Micro-Architecture Design Engineer Samsung Electronics

5.0 - 14.0 years

0 Lacs

karnataka

On-site

You have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include: - Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property - Engaging with other architects within the IP level to drive the Micro-Architectural definition - Delivering quality micro-architectural level documentation - Producing quality RTL on schedule by meeting PPA goals - Being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks - Collaborating with the verification team to ensure implementation meets architectural intent - Running quality checks such as Lint, CDC, and C...

Posted 3 weeks ago

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RTL Micro-Architecture Design Engineer Samsung Electronics

5.0 - 14.0 years

0 Lacs

karnataka

On-site

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and ...

Posted 3 months ago

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