RTL Micro-Architecture Design Engineer Samsung Electronics

5.0 - 14.0 years

0 Lacs

karnataka

On-site

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and Constraint development, debug designs in simulation environments, and have a deep understanding of fundamental concepts of digital design. Preferred skills for this role include strong Verilog/System Verilog RTL coding skills, experience with DRAM Memory Controller design, and knowledge of DRAM standard (DDR4/5) memory. Interface/Protocol experience required are AHB/AXI, Processor local bus, Flash, SPI, UART, etc. Experience with Xilinx/Intel FPGA Tool flow, knowledge of PCIe/PIPE, knowledge of projects with Microblaze, ARM cores, etc., and CXL Protocol knowledge is appreciated. To qualify for this position, you should have a Masters or Bachelors degree in Electronics or Electrical Engineering along with 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.,

Posted 2 days ago

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.