Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced SW Test and Validation Engineers to define comprehensive test plans encompassing design verification, system testing, and compliance testing for MediaTek’s most advanced Automotive products. Requirement Technical Skillset Define comprehensive test plans encompassing design verification, system testing, and compliance testing for platform and multimedia software. Drive the development of testing processes, including the definition and implementation of test system hardware and software for both manual and automated testing. Collaborate closely with both local and remote teams to diagnose and resolve issues, as well as implement automotive features. Take charge of day-to-day testing activities, including conducting sanity checks, ensuring system stability, evaluating performance, and conducting feature testing. Test exposure to Hypervisors, and Automotive Software is preferred. Test experience in Linux/QNX/RTOS/Android with exposure to Audio, CTS, DSP, NSP, and AI. Ensure strict adherence to Automotive SPICE (ASPICE) processes to maintain quality standards and compliance. Preferred programming skills in C/C++, Python, Perl, Python, and Shell. Exposure to one or more of below technology areas is a plus: Proficiency in SWE5 and SWE6 Validation and Verification methodologies. Involvement in pre/post silicon environments including early emulation/simulation, SoC bring up, post-silicon validation. Deliver monthly management updates, highlighting challenges, risks, and progress on key initiatives. Professional Experience: 3 to 15 years Show more Show less

Job Description Junior Level position with some Experience in Linux & Windows System Administration (Computing Farm, Storage, Network, OA/RD Infrastructure, etc.) Operating system and application support. End user support (include laptop/desktop deployment and support, etc.) Basic knowledge of Wired & Wireless network infrastructure Knowledge on Meeting facility/room IT infrastructure & support Asset accountability and management. Basic scripting skills are a plus Requirement Degree in Information Technology, Computer Science or equivalent 1 to 3 years of experience in IT infrastructure Setup/Support/Systems Administration is preferred Good communication, collaborative and interpersonal skills Linux/Unix system administration experience Linux/Windows virtualization Knowledge OR experience Any scripting skills is a plus Knowledge/Experience in Storage, Microsoft Windows servers, Active Directory Basic knowledge in network architecture and security Client focus, good customer service skills Willing to work over-time and standby duty, responding & normalization to Infrastructure abnormality events Able to work independently and as a team player (The capacity to work well within a team reporting to local team leader) The capacity to troubleshoot, resolve technical and applications problems on hardware and software issues Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced Engineers to understand OEMs/Tier1s requirements, architect and develop various platform SW features to enable MediaTek’s most advanced Automotive products. Requirement Professional Experience: 3 to 15 years Technical Skillset BSP/Platform SW development (PMIC/DDR/Clock, high/low speed interfaces such as UART/I2C/SPI/USB/PCIe/Ethernet etc. Experience in UEFI/Kernel driver development, Hypervisors, Virtual Machines (VMs), Virtual driver development including data isolation and permission management. Optimize boot flow, power consumption, thermal management, and overall system performance. Experience in Automotive Safety concepts, and security threat analyses to meet ISO26262, ISO21434 and ASPICE process. Additional Skills The idle candidate might have demonstrated ability to work with engineers/partners/customers across different geographies and contribute to large-scale SoC SW product development and customer support. Hands-on technical lead/engineer who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Exposure to one or more of below technology areas is a plus: Multiprocessor Architecture, ARM processors, Virtualization technologies across CPU and Peripherals, hardware accelerators Device driver development in one or more operating systems and platforms including Linux/QNX/RTOS/Android. Involvement in pre-sil/post-sil environments including early emulation/simulation, SoC bring up, post-silicon validation and troubleshooting. Show more Show less

Responsibilities include designing and developing LTE NAS/L4 modem SW, fixing defects, updating analysis results in the defect tracking system, and participating in system level analysis to debug complex issues. Requirements: - Experience in LTE or any other cellular wireless technology - Good understanding of 3GPP requirements for LTE & Multimode aspects - Experience in LTE protocol stack SW development of L4 or NAS layer - Experience in embedded software development - Programming in C/C++ - Excellent analytical and debugging skills - Desirable: Working experience of LTE Protocol stack SW development,

Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation solutions to improve efficiency in tape-out flow. Report on tapeout issues. Custom Layout Requirement Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science 5-10 years of physical verification or design experience Preferably well-versed in Calibre, ICV Proficient in script programming, such as, Tcl, Perl or C-shell Proficient in UNIX (Linux) platforms Track record of successful tapeout of chips Strong communication skills, problem solving and analytical skills

Responsibility You will be responsible for designing and developing LTE NAS/L4 modem software. Your role will involve fixing defects and updating analysis results in the defect tracking system. Additionally, you will participate in system-level analysis and debugging complex issues. Requirement Technical Skills You should have experience in LTE or any other cellular wireless technology. A good understanding of 3GPP requirements for LTE & Multimode aspects is essential. Experience in LTE protocol stack software development of L4 or NAS layer, as well as embedded software development, is required. Programming Skills Proficiency in C/C++ programming is necessary for this role. You should possess excellent analytical and debugging skills. Working experience of LTE Protocol stack software development would be desirable.,

As a Test Engineer, your primary responsibility will be to design, implement, and execute tests to validate the performance and reliability of Dual SIM design in compliance with 3GPP RRC & PHY related specifications such as TS 36.211, TS 36.212, TS 36.213, TS 36.331, TS 36.321, and project requirements. Your key responsibilities will include test planning and designing. You will develop comprehensive test plans covering all aspects of LTE/NR, incorporating the latest 3GPP Features along with elements like throughput, latency, modulation, and coding schemes. It will be your duty to design test scenarios and cases that replicate real-world conditions to ensure the robustness and reliability of the Dual SIM Protocol design. You will execute test plans both manually and through automated systems, meticulously analyzing results for compliance with the expected outcomes. Additionally, you will utilize and maintain test equipment and software tools for LTE & NR testing, including signal generators, analyzers, and simulation platforms. In the realm of test execution and automation, you will be responsible for analyzing test data to identify trends, anomalies, and areas for improvement in the Dual SIM MTK Design. Furthermore, you will prepare detailed test reports that document test procedures, results, and recommendations for enhancing performance and reliability. Your role will also necessitate a profound understanding of test systems such as CMW500, TS8980, MLAPI, Anritsu MD8430, RTD, and UXM Keysight. Therefore, proven experience in LTE/NR testing or development involving the latest 3GPP Features is essential. You are expected to possess a strong grasp of LTE/NR standards, protocols, and signal processing techniques, as well as proficiency in using LTE/NR test equipment and software tools. Excellent analytical and problem-solving skills are imperative, along with the ability to work effectively in a team and communicate complex technical information clearly. Ideally, you should have 3 to 5 years of experience in a similar role, where your expertise and skills will be instrumental in ensuring the performance and reliability of Dual SIM design through meticulous testing and analysis.,

As a Design Verification Engineer with over 5 years of experience, particularly in HBM & DDR DRAM IP and Subsystem verification, you will be an integral part of our innovative team. Your role will involve developing and executing verification plans, creating testbenches, and collaborating with design engineers to ensure high-quality and robust designs. Your responsibilities will include developing comprehensive verification plans for HBM4/4e IP and Subsystem, creating and maintaining testbenches using System Verilog and UVM methodology, performing functional verification of RTL designs, and resolving design and verification issues. You will also generate verification metrics, participate in design reviews, and stay updated with the latest verification technologies. To excel in this role, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field, have 5+ years of experience in design verification, and possess knowledge of verification languages and methodologies. Proficiency in System Verilog, UVM, and scripting languages for automation is essential. Strong problem-solving skills, attention to detail, and effective communication and teamwork abilities are crucial for success in this position. Additionally, you will be expected to mentor junior verification engineers, provide technical guidance, and contribute to the continuous improvement of verification efficiency and effectiveness. Your proven track record of successfully verifying complex IP blocks and subsystems will be highly valued in this role.,