Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced SW Test and Validation Engineers to define comprehensive test plans encompassing design verification, system testing, and compliance testing for MediaTek’s most advanced Automotive products. Requirement Technical Skillset Define comprehensive test plans encompassing design verification, system testing, and compliance testing for platform and multimedia software. Drive the development of testing processes, including the definition and implementation of test system hardware and software for both manual and automated testing. Collaborate closely with both local and remote teams to diagnose and resolve issues, as well as implement automotive features. Take charge of day-to-day testing activities, including conducting sanity checks, ensuring system stability, evaluating performance, and conducting feature testing. Test exposure to Hypervisors, and Automotive Software is preferred. Test experience in Linux/QNX/RTOS/Android with exposure to Audio, CTS, DSP, NSP, and AI. Ensure strict adherence to Automotive SPICE (ASPICE) processes to maintain quality standards and compliance. Preferred programming skills in C/C++, Python, Perl, Python, and Shell. Exposure to one or more of below technology areas is a plus: Proficiency in SWE5 and SWE6 Validation and Verification methodologies. Involvement in pre/post silicon environments including early emulation/simulation, SoC bring up, post-silicon validation. Deliver monthly management updates, highlighting challenges, risks, and progress on key initiatives. Professional Experience: 3 to 15 years Show more Show less

Job Description Junior Level position with some Experience in Linux & Windows System Administration (Computing Farm, Storage, Network, OA/RD Infrastructure, etc.) Operating system and application support. End user support (include laptop/desktop deployment and support, etc.) Basic knowledge of Wired & Wireless network infrastructure Knowledge on Meeting facility/room IT infrastructure & support Asset accountability and management. Basic scripting skills are a plus Requirement Degree in Information Technology, Computer Science or equivalent 1 to 3 years of experience in IT infrastructure Setup/Support/Systems Administration is preferred Good communication, collaborative and interpersonal skills Linux/Unix system administration experience Linux/Windows virtualization Knowledge OR experience Any scripting skills is a plus Knowledge/Experience in Storage, Microsoft Windows servers, Active Directory Basic knowledge in network architecture and security Client focus, good customer service skills Willing to work over-time and standby duty, responding & normalization to Infrastructure abnormality events Able to work independently and as a team player (The capacity to work well within a team reporting to local team leader) The capacity to troubleshoot, resolve technical and applications problems on hardware and software issues Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced Engineers to understand OEMs/Tier1s requirements, architect and develop various platform SW features to enable MediaTek’s most advanced Automotive products. Requirement Professional Experience: 3 to 15 years Technical Skillset BSP/Platform SW development (PMIC/DDR/Clock, high/low speed interfaces such as UART/I2C/SPI/USB/PCIe/Ethernet etc. Experience in UEFI/Kernel driver development, Hypervisors, Virtual Machines (VMs), Virtual driver development including data isolation and permission management. Optimize boot flow, power consumption, thermal management, and overall system performance. Experience in Automotive Safety concepts, and security threat analyses to meet ISO26262, ISO21434 and ASPICE process. Additional Skills The idle candidate might have demonstrated ability to work with engineers/partners/customers across different geographies and contribute to large-scale SoC SW product development and customer support. Hands-on technical lead/engineer who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Exposure to one or more of below technology areas is a plus: Multiprocessor Architecture, ARM processors, Virtualization technologies across CPU and Peripherals, hardware accelerators Device driver development in one or more operating systems and platforms including Linux/QNX/RTOS/Android. Involvement in pre-sil/post-sil environments including early emulation/simulation, SoC bring up, post-silicon validation and troubleshooting. Show more Show less