MediaTek

Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced SW Test and Validation Engineers to define comprehensive test plans encompassing design verification, system testing, and compliance testing for MediaTek’s most advanced Automotive products. Requirement Technical Skillset Define comprehensive test plans encompassing design verification, system testing, and compliance testing for platform and multimedia software. Drive the development of testing processes, including the definition and implementation of test system hardware and software for both manual and automated testing. Collaborate closely with both local and remote teams to diagnose and resolve issues, as well as implement automotive features. Take charge of day-to-day testing activities, including conducting sanity checks, ensuring system stability, evaluating performance, and conducting feature testing. Test exposure to Hypervisors, and Automotive Software is preferred. Test experience in Linux/QNX/RTOS/Android with exposure to Audio, CTS, DSP, NSP, and AI. Ensure strict adherence to Automotive SPICE (ASPICE) processes to maintain quality standards and compliance. Preferred programming skills in C/C++, Python, Perl, Python, and Shell. Exposure to one or more of below technology areas is a plus: Proficiency in SWE5 and SWE6 Validation and Verification methodologies. Involvement in pre/post silicon environments including early emulation/simulation, SoC bring up, post-silicon validation. Deliver monthly management updates, highlighting challenges, risks, and progress on key initiatives. Professional Experience: 3 to 15 years Show more Show less

Job Description Junior Level position with some Experience in Linux & Windows System Administration (Computing Farm, Storage, Network, OA/RD Infrastructure, etc.) Operating system and application support. End user support (include laptop/desktop deployment and support, etc.) Basic knowledge of Wired & Wireless network infrastructure Knowledge on Meeting facility/room IT infrastructure & support Asset accountability and management. Basic scripting skills are a plus Requirement Degree in Information Technology, Computer Science or equivalent 1 to 3 years of experience in IT infrastructure Setup/Support/Systems Administration is preferred Good communication, collaborative and interpersonal skills Linux/Unix system administration experience Linux/Windows virtualization Knowledge OR experience Any scripting skills is a plus Knowledge/Experience in Storage, Microsoft Windows servers, Active Directory Basic knowledge in network architecture and security Client focus, good customer service skills Willing to work over-time and standby duty, responding & normalization to Infrastructure abnormality events Able to work independently and as a team player (The capacity to work well within a team reporting to local team leader) The capacity to troubleshoot, resolve technical and applications problems on hardware and software issues Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced Engineers to understand OEMs/Tier1s requirements, architect and develop various platform SW features to enable MediaTek’s most advanced Automotive products. Requirement Professional Experience: 3 to 15 years Technical Skillset BSP/Platform SW development (PMIC/DDR/Clock, high/low speed interfaces such as UART/I2C/SPI/USB/PCIe/Ethernet etc. Experience in UEFI/Kernel driver development, Hypervisors, Virtual Machines (VMs), Virtual driver development including data isolation and permission management. Optimize boot flow, power consumption, thermal management, and overall system performance. Experience in Automotive Safety concepts, and security threat analyses to meet ISO26262, ISO21434 and ASPICE process. Additional Skills The idle candidate might have demonstrated ability to work with engineers/partners/customers across different geographies and contribute to large-scale SoC SW product development and customer support. Hands-on technical lead/engineer who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Exposure to one or more of below technology areas is a plus: Multiprocessor Architecture, ARM processors, Virtualization technologies across CPU and Peripherals, hardware accelerators Device driver development in one or more operating systems and platforms including Linux/QNX/RTOS/Android. Involvement in pre-sil/post-sil environments including early emulation/simulation, SoC bring up, post-silicon validation and troubleshooting. Show more Show less

Responsibilities include designing and developing LTE NAS/L4 modem SW, fixing defects, updating analysis results in the defect tracking system, and participating in system level analysis to debug complex issues. Requirements: - Experience in LTE or any other cellular wireless technology - Good understanding of 3GPP requirements for LTE & Multimode aspects - Experience in LTE protocol stack SW development of L4 or NAS layer - Experience in embedded software development - Programming in C/C++ - Excellent analytical and debugging skills - Desirable: Working experience of LTE Protocol stack SW development,

Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation solutions to improve efficiency in tape-out flow. Report on tapeout issues. Custom Layout Requirement Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science 5-10 years of physical verification or design experience Preferably well-versed in Calibre, ICV Proficient in script programming, such as, Tcl, Perl or C-shell Proficient in UNIX (Linux) platforms Track record of successful tapeout of chips Strong communication skills, problem solving and analytical skills

Responsibility You will be responsible for designing and developing LTE NAS/L4 modem software. Your role will involve fixing defects and updating analysis results in the defect tracking system. Additionally, you will participate in system-level analysis and debugging complex issues. Requirement Technical Skills You should have experience in LTE or any other cellular wireless technology. A good understanding of 3GPP requirements for LTE & Multimode aspects is essential. Experience in LTE protocol stack software development of L4 or NAS layer, as well as embedded software development, is required. Programming Skills Proficiency in C/C++ programming is necessary for this role. You should possess excellent analytical and debugging skills. Working experience of LTE Protocol stack software development would be desirable.,

As a Test Engineer, your primary responsibility will be to design, implement, and execute tests to validate the performance and reliability of Dual SIM design in compliance with 3GPP RRC & PHY related specifications such as TS 36.211, TS 36.212, TS 36.213, TS 36.331, TS 36.321, and project requirements. Your key responsibilities will include test planning and designing. You will develop comprehensive test plans covering all aspects of LTE/NR, incorporating the latest 3GPP Features along with elements like throughput, latency, modulation, and coding schemes. It will be your duty to design test scenarios and cases that replicate real-world conditions to ensure the robustness and reliability of the Dual SIM Protocol design. You will execute test plans both manually and through automated systems, meticulously analyzing results for compliance with the expected outcomes. Additionally, you will utilize and maintain test equipment and software tools for LTE & NR testing, including signal generators, analyzers, and simulation platforms. In the realm of test execution and automation, you will be responsible for analyzing test data to identify trends, anomalies, and areas for improvement in the Dual SIM MTK Design. Furthermore, you will prepare detailed test reports that document test procedures, results, and recommendations for enhancing performance and reliability. Your role will also necessitate a profound understanding of test systems such as CMW500, TS8980, MLAPI, Anritsu MD8430, RTD, and UXM Keysight. Therefore, proven experience in LTE/NR testing or development involving the latest 3GPP Features is essential. You are expected to possess a strong grasp of LTE/NR standards, protocols, and signal processing techniques, as well as proficiency in using LTE/NR test equipment and software tools. Excellent analytical and problem-solving skills are imperative, along with the ability to work effectively in a team and communicate complex technical information clearly. Ideally, you should have 3 to 5 years of experience in a similar role, where your expertise and skills will be instrumental in ensuring the performance and reliability of Dual SIM design through meticulous testing and analysis.,

As a Design Verification Engineer with over 5 years of experience, particularly in HBM & DDR DRAM IP and Subsystem verification, you will be an integral part of our innovative team. Your role will involve developing and executing verification plans, creating testbenches, and collaborating with design engineers to ensure high-quality and robust designs. Your responsibilities will include developing comprehensive verification plans for HBM4/4e IP and Subsystem, creating and maintaining testbenches using System Verilog and UVM methodology, performing functional verification of RTL designs, and resolving design and verification issues. You will also generate verification metrics, participate in design reviews, and stay updated with the latest verification technologies. To excel in this role, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field, have 5+ years of experience in design verification, and possess knowledge of verification languages and methodologies. Proficiency in System Verilog, UVM, and scripting languages for automation is essential. Strong problem-solving skills, attention to detail, and effective communication and teamwork abilities are crucial for success in this position. Additionally, you will be expected to mentor junior verification engineers, provide technical guidance, and contribute to the continuous improvement of verification efficiency and effectiveness. Your proven track record of successfully verifying complex IP blocks and subsystems will be highly valued in this role.,

Join a dynamic software engineering team at ISD's India site, focusing on Client Computing and Automotive projects involving technologies such as Camera, Video, Power, Audio kernel mode driver, and UEFI development. You will be responsible for evaluating and implementing performance and power optimizations across the platform and contributing to various software technologies for high-performance integrated circuits. The ideal candidate should possess excellent C/C++ programming skills and a strong understanding of debugging methodologies, software engineering practices, unit-testing, and static analysis. Experience in developing software in an Agile environment is required. Additionally, a good grasp of computer architecture, operating system fundamentals, UEFI, EDK2, ACPI, SMBIOS, and RAS features is essential. Candidates should have the ability to interpret schematics and hardware programming guides effectively. A successful candidate will be a collaborative team player, self-motivated, and approach tasks with a positive attitude.,

Job Description Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies. Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations. 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips. Familiar with programming languages: C, C++, and/or SystemC. Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus. Requirement Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. Document on new flows and processes for AMS DV. Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Job Description Your responsibilities will include the specification, architecture design, circuit design, implementation and verification of complete sub-systems for 5G RF ICs. Your focus will be on developing innovative signal path or synthesizer designs with leading edge performance and excellent results on first silicon. Requirement Masters' graduate or PhD in a closely related field Minimum 5 Years Relevant Industrial Experience Proven track record of delivering high performance CMOS RF transceivers to mass production Excellent knowledge of RF system analysis and able to work effectively with RF System and Application Engineers to define the specification Experience with design in advanced CMOS technologies (16nm or below) Strong analytical skills Excellent grasp of the integration challenges of complex RF systems-on-a-chip (SoCs) Expertise in RF IC layout optimization in advanced CMOS technologies and be able to provide effective supervision for layout implementation An innovative thinker with a passion for challenging technical problem solving A strong team player able to collaborate on complex projects as well as successfully working independently Able to communicate effectively with people across different timezones and cultures Excellent time management and organisation skills

Job Description Architecture study and evaluation of advanced SerDes topologies SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc. Evaluate, measure, and debug silicon until it reaches high volume production. Work with cross functional teams to optimize the designs. Requirement MS or Ph.D with a major in EE or Physics related field. Solid background in analog CMOS circuit design. Proficient with Cadence design environment and mixed-signal simulation. Able to assume responsibility for a variety of technical tasks and to work independently. (recommended) Digital communication system, digital signal processing, digital system design, RF system, MATLAB

SoC/IP Verification Engineer : Team Functional SoC Verification team for MediaTek’s TV/Automotive/5G/other advanced SoC development Roles Close co-work with global teams to define/verify new features for Mediatek next-gen SoC products Mentor cross-domain teams to achieve the verification goals Responsible for enhancing/developing SoC test plans and verification methodologies. Be the domain expert to facilitate and set verification guidelines for global teams Opportunity to interact with top management for SoC verification related expert opinions Drive internal and 3rd party resources to build a strong SoC expertise at MediaTek Bangalore Additional Responsibilities Collaborate with global RTL, SW and other platform teams for feature definition and quality assurance Interact with SW teams to ensure that the verification Plan is as close as possible to real life scenario Ensure the Quality of deliverables with coverage metrics, scenarios and sufficient checks Updates and proposals to top management Requirements B.Tech/M.Tech with 3-15 years of experience as a Functional verification Engineer with prior SoC Verification Experience. Excellent hands-on coding proficiency on SV and C is a must. Perl or Python coding skills are desirable. Hands-on experience in developing verification env, proficiency in CPU architecture, C, assembly language Able to understand SoC Architectural spec and define SoC TB architecture. Familiarity with UPF based power aware simulations and GLS is desirable. Opportunities Cutting edge work on next generation SoC Verification

The ideal candidate for this role should hold a BE/B.Tech/ME/M.Tech degree in EEE/ECE/CSE with 5-12 years of relevant industry experience. You should have a strong background in verification methodology and be proficient in architecting and developing testbench components for ISA features, clock/reset/power features of processors. Your expertise should include a deep understanding of assembly and CPU architecture, particularly in x86/ARM/RISC-V. Proficiency in programming languages such as C, C++, Verilog, and scripting languages like Perl and Python is essential. You should be able to work independently and collaborate effectively across different geographies. Main responsibilities of this role include working closely with CPU architects to comprehend processor micro-architecture, developing detailed test and coverage plans for ISA and micro-architecture features, designing and implementing component, block, and core level testbenches, and building architectural tools for ISA level verification. You will be expected to create stimulus generators that can be utilized across various domains ranging from pre-silicon to emulation and post-silicon. Additionally, you will execute verification plans, conduct DV environment bring-up, enable regression for all features under your responsibility, and troubleshoot test failures. Tracking and reporting DV progress using metrics like bugs and coverage will also be a key part of your role. Preferred qualifications for this position include in-depth knowledge of processor verification function and architecture, particularly in areas like cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation. Experience in Random Instruction Sequencing (RIS) and testing at block/unit and chip levels is highly valued. Leading a team of verification engineers in CPU verification, proficiency in advanced techniques like formal, assertions, and silicon bring up, and experience in writing test plans, portable benches, transactors, and assembly are also preferred. Familiarity with various verification methodologies and tools such as simulators, coverage collection, and gate-level simulation is advantageous. The ability to independently develop test benches for a block/unit of the design is a desired skill for this role.,

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

Your responsibilities will encompass the specification, architecture design, circuit design, implementation, and verification of complete sub-systems for 5G RF ICs. You will primarily focus on developing innovative signal path or synthesizer designs to achieve leading-edge performance and ensure excellent results on first silicon. You should hold a Masters" graduate or PhD in a closely related field and have a minimum of 5 years of relevant industrial experience. A proven track record of delivering high-performance CMOS RF transceivers to mass production is essential for this role. Your expertise in RF system analysis should allow you to collaborate effectively with RF System and Application Engineers to define the specification. Experience with design in advanced CMOS technologies, specifically 16nm or below, is required. You must possess strong analytical skills and an excellent grasp of the integration challenges of complex RF systems-on-a-chip (SoCs). Your expertise in RF IC layout optimization in advanced CMOS technologies will enable you to provide effective supervision for layout implementation. As an innovative thinker with a passion for challenging technical problem-solving, you should thrive in a collaborative environment. Strong team player skills are necessary for successful collaboration on complex projects, as well as the ability to work independently. Effective communication with individuals across different time zones and cultures is crucial. Your excellent time management and organization skills will be invaluable in meeting project deadlines and delivering high-quality results.,

The IT Engineer position is ideal for someone at the Junior Level with some Experience in Linux & Windows System Administration. Your responsibilities will include providing support for Operating system and applications, end user support (including laptop/desktop deployment), and basic Wired & Wireless network infrastructure knowledge. Additionally, you will be involved in Meeting facility/room IT infrastructure & support, asset accountability and management, and basic scripting tasks. To qualify for this role, you should have a degree in Information Technology, Computer Science, or a related field, along with 1 to 3 years of experience in IT infrastructure Setup/Support/Systems Administration. Good communication, collaborative, and interpersonal skills are essential. Experience in Linux/Unix/ Microsoft Windows system administration, virtualization, scripting, Storage, Microsoft Windows servers, and Active Directory is preferred. Basic knowledge in network architecture and security, client focus, and customer service skills are also necessary. You should be willing to work over-time and standby duty to respond & normalize IT Infrastructure abnormality events. The ability to work independently and as a team player is crucial, as well as troubleshooting and resolving technical and applications problems. Your tasks may involve RD Thin Client and Remote access Infrastructure management & support, OA (Office Applications) Infrastructure support backup role, and Data Center operations with vendor coordination. Overall, this role requires a proactive individual who can handle various IT infrastructure tasks effectively and efficiently while maintaining a high level of service and support.,

Job Description Join a dynamic SW engineering team for ISD’s India site for Client Computing and Automotive efforts involving key technologies which may involve Camera, Video, Power, Audio kernel mode driver development. Evaluate and drive performance and power optimizations on overall platform. Contribute to a variety of software technologies high performance integrated circuits. Requirement Experience developing software in an Agile environment. Experience developing low-level, driver, or kernel components for modern high-level operating systems. Strong understanding of software engineering practices, unit-testing, static analysis, etc… Ability to understand schematics and hardware programming guides. Experience with issue tracking systems (for example Jira) and reporting software (for example PowerBI) is a bonus. Good C++ programming skills. Experience with various software components - BIOS, ACPI, UEFI, Drivers is a plus.

Job Description Key Qualifications Preferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience. Should have experience in verification methodology. Architecting and development of testbench, test-bench components for ISA features, clock/reset/power features of processor. Strong assembly and CPU (x86/ARM/RISC-V) architecture knowledge. Strong in C, C++, Verilog, and scripting (Perl, Python) languages. Ability to work independently and across geographies Requirement Role and Responsibilities Work with CPU architects to get understand processor micro-architecture Develop detailed test and coverage plans for ISA and micro-architecture features Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers Build architectural tools for ISA level verification Develop stimulus generators that scale from pre-silicon to emulation and post-silicon domain Execute verification plans, including DV environment bring-up, regression enabling for all features under your care, debug of the test failures Track and report DV progress using a variety of metrics, including bugs and coverage Preferred Qualifications Deep knowledge in processor verification function and architecture, in areas such as cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation Knowledge in Random Instruction Sequencing (RIS) and testing associated as block/unit and chip level for proving correctness Have lead a small team of verification engineers doing CPU verification Advanced techniques such as formal, assertions, and silicon bring up a plus Experience in writing test plans, portable benches, transactors, and assembly Experience with many different verification methodologies and tools such as simulators, coverage collection, gate level simulation Able to develop test bench and work independently on a block/unit of the design