Job
Description
The ideal candidate for this role should hold a BE/B.Tech/ME/M.Tech degree in EEE/ECE/CSE with 5-12 years of relevant industry experience. You should have a strong background in verification methodology and be proficient in architecting and developing testbench components for ISA features, clock/reset/power features of processors. Your expertise should include a deep understanding of assembly and CPU architecture, particularly in x86/ARM/RISC-V. Proficiency in programming languages such as C, C++, Verilog, and scripting languages like Perl and Python is essential. You should be able to work independently and collaborate effectively across different geographies. Main responsibilities of this role include working closely with CPU architects to comprehend processor micro-architecture, developing detailed test and coverage plans for ISA and micro-architecture features, designing and implementing component, block, and core level testbenches, and building architectural tools for ISA level verification. You will be expected to create stimulus generators that can be utilized across various domains ranging from pre-silicon to emulation and post-silicon. Additionally, you will execute verification plans, conduct DV environment bring-up, enable regression for all features under your responsibility, and troubleshoot test failures. Tracking and reporting DV progress using metrics like bugs and coverage will also be a key part of your role. Preferred qualifications for this position include in-depth knowledge of processor verification function and architecture, particularly in areas like cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation. Experience in Random Instruction Sequencing (RIS) and testing at block/unit and chip levels is highly valued. Leading a team of verification engineers in CPU verification, proficiency in advanced techniques like formal, assertions, and silicon bring up, and experience in writing test plans, portable benches, transactors, and assembly are also preferred. Familiarity with various verification methodologies and tools such as simulators, coverage collection, and gate-level simulation is advantageous. The ability to independently develop test benches for a block/unit of the design is a desired skill for this role.,
