3 Cpu Architecture Jobs

Key Responsibilities: Verification Planning & Execution: Develop comprehensive verification plans for CPU cores and related components, including functional verification, performance verification, and edge-case testing. Design and implement testbenches for CPU verification using SystemVerilog, UVM, or other relevant verification methodologies. Perform functional simulation, debugging, and analysis to identify and resolve design issues or bugs. Test Development: Write and maintain test cases for different aspects of CPU functionality, including control logic, pipelines, cache systems, and other subsystems. Create directed and random test scenarios to validate different modes of operation, handling of exceptions, interrupts, and other critical events. Work on functional, performance, and stress testing to ensure the CPU design meets the required benchmarks. Simulation & Debugging: Run simulations on testbenches, monitor waveform outputs, and analyze results to identify discrepancies between expected and actual CPU behavior. Use debugging tools and techniques (e.g., waveform viewers, code coverage, assertions) to track down issues and drive them to resolution. Collaborate with the design team to troubleshoot and resolve failures in the design or verification process. Performance and Power Verification: Verify CPU performance through benchmark testing and performance analysis. Work with the architecture team to analyze and optimize CPU power consumption and verify power-related aspects of the design. Conduct stress and corner-case testing to identify performance bottlenecks. Collaboration with Cross-functional Teams: Work closely with architecture, RTL design, and validation teams to ensure alignment between the verification environment and CPU architecture. Participate in design reviews, ensuring that verification requirements are considered and covered in the CPU design. Provide feedback to the design team regarding improvements to architecture and implementation for better verification coverage.

In this position, the candidate will be responsible for designing soft IP cores for Intel's next generation chips for different market segments. Qualifications Minimum Qualification Master of Science (or a Master of Technology) degree in Electrical Engineering with 6 years of relevant industry experience. Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with 8 years of relevant industry experience. Relevant ASIC design experience in front end processes including RTL development, Unit verification with assertions. Expertise in design, development, and integration of design blocks (IP) Expertise in Verilog and system Verilog based logic design Experience in synthesis flow and timing closure Experience in one/more of the following areas PCI, PCI_Express (RAS), AMBA standards (AXI, AHB, etc..) would prefer Knowledge of SVA and associated tools. Jasper, etc Knowledge of memory controllers and CPU architecture is a plus Looking for highly motivated individuals with the ability to deal with ambiguity Knowledge of considerations for performance, power, cost optimization, as well as design integrity for physical implementation is desirable Relevant experience in chip design with familiarity with the entire development flow from definition to Tape-Out. Good Problem-Solving Ability. Ability to work in a team environment.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable