Job Description : Join our Cambridge team as a Graduate Software Engineer and enter the cutting-edge world of 5G & 6G semiconductor technology. You'll design, implement, and verify innovative bespoke software, including our sophisticated simulation of a real 5G network. Our powerful software helps MediaTek global R&D to develop and validate embedded software for smartphones, IoT devices, and automotive chips - from pre-silicon to complex field-test scenarios. We are using AI and automation to make our tools faster, easier to use and cover more complicated use-cases. Our small, friendly local team collaborates with engineers around the world to provide feature-rich Windows GUIs, automated Linux & terminal server backend automation and more. If you're passionate about solving tough engineering challenges with software and excited about shaping the future of mobile communications, we want to hear from you! Key Responsibilities: .Software Development: Develop and enhance advanced tools for Linux and Windows environments using C++, C#, and/or Python. .Global Collaboration: Work closely with R&D teams in the UK, Finland, Taiwan, China, and India, exploring requirements, sharing knowledge and satisfying global chipset projects. .AI/ML Integration: Adding AI/ML enhancements to sophisticated tool chains, improving efficiency, accuracy and automatic monitoring. .Data Management: Use robust, scalable databases to store, manage, and analyze TBs of data. .Dashboard & Visualizations: Create and refine web-based dashboards using HTML and JavaScript to present sophisticated data visualizations and insights to users. .Protocol Exposure: Work with 5G, and emerging 6G protocol software, gaining insight into the core technologies driving modern mobile communications. .Innovation: Identify opportunities to innovate and influence the evolution of our tools, processes, and technologies, making a tangible impact on a global scale. Job Requirement: You'll have: .Graduated in Computer Science, Software Engineering, or a related discipline. .Strong programming skills in at least one object-oriented language (e.g., Java, C++, C#, Python). .Passion for software development and problem-solving. .An ability to learn new technologies quickly and work effectively both independently and as part of a team. .Excellent communication skills and a collaborative mindset. What We Offer: .A full-time, permanent position in our modern open-plan R&D Center near Cambridge. .The opportunity to work on real, impactful projects in a leading global high-tech company. .Collaboration with experienced and diverse engineers in a friendly, supportive team environment. .Opportunities to interact and network with R&D colleagues around the world. .Exposure to a wide range of programming languages, tools, and technologies, supporting your professional growth. .Competitive salary and benefits package. .A flexible and inclusive workplace that values innovation, learning, and personal development. Location This role will be based at our Cambourne office, based 9 miles from Cambridge city centre (with frequent direct bus services). MediaTek and You MediaTek is the world's 4th largest global fabless semiconductor company. We are market leaders in developing innovative systems-on-chip (SoC) for mobile device, home entertainment, connectivity and IoT products. Ultimately, we power more than 2 billion devices a year. Our engineers have a great passion and work ethic, have a broad set of technical skills and are ready to master new technologies and tackle some of industry's greatest challenges. We pride ourselves on our global collaborative team culture and a competitive compensation package. We know that each person makes important contributions, and that they are integral to our success. Competitive Package Available Closing Date - 28-Sept-2025 #LI-AK1
Job Description : KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure. Job Requirement: PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/PrimeClosure, Innovus Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV,AOCV,POCV analysis Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering
Job Description : Sub System Verification Lead : Team- Functional subsystem Verification team for MediaTek's TV/Automotive/5G/other advanced SoC development Roles Close co-work with global teams to define/verify new features for Mediatek next-gen SoC products Mentor cross-domain teams to achieve the verification goals Responsible for enhancing/developing subsys/SoC test plans and verification methodologies specific to a subsys. Be the domain expert to facilitate and set verification guidelines for global teams Opportunity to interact with top management for subsys verification related expert opinions Drive internal and 3rd party resources to build a strong subsys expertise at MediaTek Bangalore Additional Responsibilities Collaborate with global RTL, SW and other platform teams for feature definition and quality assurance Interact with SW teams to ensure that the verification Plan is as close as possible to real life scenario Ensure the Quality of deliverables with coverage metrics, scenarios and sufficient checks Updates and proposals to top management Job Requirement: Requirements B.Tech/M.Tech with 8-15 years of experience as a Functional verification Engineer with prior SoC Verification Experience. Excellent hands-on coding proficiency on SV and C is a must. Perl or Python coding skills are desirable. Hands-on experience in developing verification env, proficiency in CPU architecture, C, assembly language Able to understand SoC Architectural spec and define SoC TB architecture. Familiarity with UPF based power aware simulations and GLS is desirable. Opportunities Opportunity to architect and develop subsys level test benches from scratch. Cutting edge work on next generation SoC Verification
Job Description : Senior Staff Engineer - Power Integrity / IR drop analysis Job Description The PI Signoff / IR Drop Analysis Lead is responsible for Signoff level IR drop, Power/Signal EM analysis of a Subsystem and Full SoC. He is responsible for running EM and Static/Dynamic IR analysis for various modes/power scenarios, root cause failures, provide fixing solutions. He should follow/define best practices and strategy as per technology node. He contributes to problem solving related to overall PI analysis. Responsibilities include EM and IR drop analysis (vector and vectorless) for both block and full chip designs for various power modes and scenarios. Provide feedback / improvement / fixing suggestions to various stake holders like owners for Power, package, pattern, physical design, timing, etc Analyze weakness area(s) in the design and provide fixing solutions. Automation for reporting, debug, fixing suggestions/ECOs. Setting up and Maintaining the environment for the overall PI analysis Provide training to junior folks in the team to enhance their productivity and to extract quality work The candidate must have: 8+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysis Hands-on experience on RedHawk-SC or Voltus, preferably both Hands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designs Experience in leading block level or chip level IR/EM analysis Ability to debug and resolve issues with inputs like - design data, library info, package, bump locations/RDL routing Automation skills in TCL/Perl/awk/Python/Unix shell Team player who is able to autonomously plan and perform tasks Experience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the job Worked on technologies 16nm and below, preferably on N7 and lower nodes Exposure on designing power mesh especially on low power, power shut off designs Some exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime) Job Requirement: The candidate must have: 8+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysis Hands-on experience on RedHawk-SC or Voltus, preferably both Hands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designs Experience in leading block level or chip level IR/EM analysis Ability to debug and resolve issues with inputs like - design data, library info, package, bump locations/RDL routing Automation skills in TCL/Perl/awk/Python/Unix shell Team player who is able to autonomously plan and perform tasks Experience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the job Worked on technologies 16nm and below, preferably on N7 and lower nodes Exposure on designing power mesh especially on low power, power shut off designs Some exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime)
Job Description : Job Function Functional Formal Verification Engineer - Lead We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs. Qualifications: . Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. . 5+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. . Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL. . Experience with industry-standard EDA formal tools. . Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. . Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. . Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. . Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. Responsibilities . Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. . Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. . Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. . Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. . Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. . Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. Preferred Skills: . Experience with CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). . Familiarity with UVM methodology and/or other simulation-based verification methodologies. . Experience with advanced FV performance optimization techniques, such as abstraction methods, property decomposition, and other state-space reduction techniques. . Expertise in Jasper or VC Formal products is highly desirable. Job Locations . India: Bangalore Job Requirement: Job Function Functional Formal Verification Engineer - Lead We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs. Qualifications: . Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. . 5+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. . Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL. . Experience with industry-standard EDA formal tools. . Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. . Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. . Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. . Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. Responsibilities . Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. . Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. . Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. . Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. . Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. . Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. Preferred Skills: . Experience with CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). . Familiarity with UVM methodology and/or other simulation-based verification methodologies. . Experience with advanced FV performance optimization techniques, such as abstraction methods, property decomposition, and other state-space reduction techniques. . Expertise in Jasper or VC Formal products is highly desirable. Job Locations . India: Bangalore