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Technical Lead - Design Verification (SV UVM) Thales

8.0 - 12.0 years

30 - 40 Lacs

Bengaluru

Work from Office

Hi, Greetings from Thales India Pvt Ltd.....! We are hiring for Technical Lead - Design Verification (SV UVM) for our Engineering competency center for Bangalore location. Thales India Engineering Competency Center in Bangalore is seeking Technical Lead /Senior Technical Lead role to be part of AVS/FLX FPGA design and development team. In this role, you will be responsible for FPGA Validation & Verification for Avionics products and solutions. Responsibilities includes development of Test strategy, Virtual Verification Procedures, Test bench, BFMs, Monitors, Checkers & Virtual Verification Report as per DO254 guidelines. Qualifications: B.Tech/B.E or Masters in Electronics & Communication or equivalent with 8 to 12 years of relevant experience. Working experience in Defence\military\Aerospace products development is desirable Location: Thales India Private Limited, Richmond Town, Bengaluru, Karnataka 560025. Required Skills: Mandatory: Hands on in FPGA device Validation and Verification methodologies and processes. Experience in developing verification strategies and creating test plan based on requirements. Hands on Virtual Verification Environment development using VHDL and System Verilog/UVM Should be experienced in BFM development, monitors, checkers and Test case development using VHDL and SV/UVM Hands on with physical verification methodologies for various FPGA devices Good experience in Requirements Capture, developing Design Specification, Detailed design, Test procedure, Test report & other technical artefacts. Hands on experience in performing simulations using the Questasim tool. Should be hands on with configuration management tools such as GIT, BIT Bucket, DOORS, GIT/BIT Bucket/ REQTIFY/DOORS Good experience in RTL Design using VHDL, FPGA Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense\military\Aerospace Applications. Experience in any scripting language for automation, such as Python, Perl or TCL Experienced with Jenkins for continuous integration and automation of test and build processes. Capable of independently managing project planning, estimation, scheduling, technical risk identification and mitigation. Experience in Intel, Microchip or Xilinx based FPGA/PLD will have added advantage Experience in Bus Interfaces - A818, A429, SPI/UART/I2C, PCIe, AXI4, A664, LVDS, DDRx Should be experienced with environment to work in a cross-functional and multi-national global team. Expected to be Familiar: Experience in FPGA validation and verification in line with DO-254 process Experience in FPGA Implementation Tools (XILINX Vivado/ALTERA Libero SoC/ ALTERA Quartus). Experience in JIRA (Project / Issue management) Experience in handling Lab equipment (Logic Analyzer, Oscilloscope, Function Generators, JTAG, and In-circuit de-buggers).

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R&D Engineering, Sr Staff Engineer (VIP verification) Synopsys

7.0 - 12.0 years

7 - 13 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

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Steel Detailers/ Checkers- SDS/2 Cadeploy Engineering

3.0 - 8.0 years

4 - 8 Lacs

Hyderabad

Work from Office

Hey all, Were Hiring: Experienced Steel Detailers & Checkers- SDS/2 Location: Hyderabad We are looking for experienced Steel Detailers & Checkers with strong expertise in SDS /2 Software - AISC (Exp: 3+ Years). If you have hands-on expertise with SDS/2 and a passion for precision in Steel detailing, wed love to hear from you! Please send your resume to gdivyasri@cadeploy.com Feel free to share this opportunity with your network! Join us and be part of a growing, dynamic team at Cadeploy Engineering!

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