Masters graduate or PhD in a closely related fieldMinimum 5 years relevant industrial experienceProven track record of delivering high performance CMOS RF transceivers to mass productionExcellent knowledge of RF system analysis and able to work effectively with RF System and Application Engineers to define the specification Experience with design in advanced CMOS technologies (16nm or below)Strong analytical skills Excellent grasp of the integration challenges of complex RF systems-on-a-chip (SoCs) Expertise in RF IC layout optimization in advanced CMOS technologies and be able to provide effective supervision for layout implementation An innovative thinker with a passion for challenging technical problem solving A strong team player able to collaborate on complex projects as well as successfully working independently Able to communicate effectively with people across different timezones and culturesExcellent time management and organisation skills Your responsibilities will include the specification, architecture design, circuit design, implementation and verification of complete sub-systems for 5G RF ICs Your focus will be on developing innovative signal path or synthesizer designs with leading edge performance and excellent results on first silicon
MS or Ph D with a major in EE or Physics related field Solid background in analog CMOS circuit design Proficient with Cadence design environment and mixed-signal simulation Able to assume responsibility for a variety of technical tasks and to work independently (recommended) Digital communication system, digital signal processing, digital system design, RF system, MATLAB Architecture study and evaluation of advanced SerDes topologies SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc Evaluate, measure, and debug silicon until it reaches high volume production Work with cross functional teams to optimize the designs
Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration Document on new flows and processes for AMS DV Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support Quick learner with strong critical thinking and creative problem-solving skills Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA) Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips Familiar with programming languages: C, C++, and/or SystemC Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e g, CVS, Perforce, etc) is a plus Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plusDesign or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc, is a plus
Requirements :Bachelors or Masters Degree with a strong VLSI BackgroundMinimum 3 years of experience in the area of Synthesis Synthesis Engineer: (3-10 Years)Key Responsibilities:Synthesis Environment setupValidating synthesis SDC qualityUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node Checking the synthesis DEF qualityAnalyze critical timing violation groups and congestion solve them by finetune floorplan or placement constraints Compare area/power with previous projects and check current project results DFT Insertion and debugging basic DFT issues Discuss directly with Design teams & Physical design teams to get the best synthesis results
RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure
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