Design and Verification Engineer

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Role Overview

The Design Verification Engineer is responsible for ensuring that digital hardware designs meet functional specifications and quality standards before tape-out or production. This role involves developing and executing verification plans, creating testbenches, and using simulation and formal verification techniques to validate the correctness of complex integrated circuits (ICs), SoCs, or FPGA designs.

Key Responsibilities

• Verification Planning

  : Define and document verification strategies, test plans, and coverage goals based on design specifications.

• Testbench Development

  : Build and maintain reusable, modular testbenches using industry-standard methodologies (e.g., UVM, SystemVerilog).

• Simulation & Debugging

  : Run simulations, analyze waveforms, and debug failures to identify design or testbench issues.

• Coverage Analysis

  : Track functional and code coverage metrics to ensure completeness of verification.

• Regression Management

  : Set up and maintain automated regression environments for continuous verification.

• Collaboration

  : Work closely with design engineers, architects, and other teams to clarify requirements and resolve issues.

• Tool Utilization

  : Use EDA tools for simulation, linting, formal verification, and coverage analysis.

• Documentation

  : Prepare detailed reports on verification progress, coverage, and bug tracking.

Required Skills

• Strong knowledge of

  digital design concepts

  (RTL, timing, protocols).
• Proficiency in

  HDLs

  (Verilog/SystemVerilog) and verification methodologies (UVM).
• Familiarity with

  simulation tools

  (e.g., VCS, Questa, Xcelium) and scripting languages (Python, Perl, Shell).
• Understanding of

  coverage-driven verification

  and debugging techniques.
• Excellent problem-solving and communication skills.

Preferred Qualifications

• Experience with

  formal verification

  ,

  low-power verification

  , or

  emulation/prototyping

  .
• Knowledge of

  industry-standard protocols

  (AXI, PCIe, Ethernet, etc.).
• Exposure to

  continuous integration

  and regression automation.