136 Functional Verification Jobs

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Master's Degree Required technical and professional expertise 6 + years of experience in Functional Verification of processors or ASICs. 3+ years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodology like UVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Good understanding of computer system architecture and microarchitecture.

Job Specs : Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit.

Role Overview: You will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation of products used by millions globally. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering high performance, efficiency, and integration. The Platforms and Devices team at Google works on various computing software platforms and first-party devices, combining Google AI, software, and hardware to create innovative user experiences worldwide. Key Responsibilities: - Contribute to Central Processing Unit (CPU) front-end designs, emphasizing microarchitecture and Register-Transfer Level (RTL) design for the next-generation CPU. - Propose efficient and performance-enhancing microarchitecture features, collaborating with architects and performance teams to conduct trade-off studies and communicate the advantages and disadvantages for final decision-making. - Ensure designs meet Power, Performance, and Area (PPA) goals with production quality. - Familiarize yourself with techniques for at least one processor functional block, translating these techniques into design constructs and languages to provide guidance and participate in the performance modeling effort. - Collaborate closely with the functional verification team to ensure production quality designs and work with the physical design team to achieve frequency, power, and area goals. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience in microprocessor architecture through coursework or industry experience. - Experience in logic design through coursework or industry experience. - Masters or PhD degree in Electrical Engineering or Computer Science (preferred). - Experience with modern processor microarchitecture, related technologies, and algorithms through academic projects or industry experience. - Knowledge of programming languages such as C, C++, and Python. - Knowledge of general-purpose operating systems like Linux or Android.,

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Job Details Job Description: Come join Intel&aposs Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms. Your Responsibilities Will Include But Not Be Limited To Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA. Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide. Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause. Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design. Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models. Developing debugging tools and software. Qualifications Minimum Qualifications: Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience. Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others. Proven record of working across verification teams to solve problems. Expert of HW and SW Interaction and debug to root cause. Experience working across verification, architecture, SW, and design teams to resolve debug issues. Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans. Minimum 4years of SOC Verification or Functional verification. Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux. Minimum 2yrs experience with SOC Architecture. Must have 4yrs+ experience with SOC Verification or Functional Verification. Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team. Preferred Qualifications Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture. Good to have working experience on assertions, coverage and Formal verification Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel&aposs PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people&aposs potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem, or full-chip level. Define and implement constrained-random, directed, and coverage-driven verification methodologies (UVM/SystemVerilog preferred). Develop and maintain scalable and reusable testbench components. Mentor and guide junior verification engineers in testbench architecture, debugging, and coverage closure. Collaborate with RTL designers, architects, and firmware/software teams to understand design intent and develop test plans. Own and track functional coverage metrics and ensure 100% coverage goals are met. Drive regular reviews of verification status, risks, and issues with stakeholders. Support post-silicon validation teams with test vectors, debugging, and failure analysis. Required Qualifications: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of industry experience in digital design verification. Strong expertise in SystemVerilog, UVM, and advanced verification methodologies. Experience in testbench architecture, test planning, and constrained-random stimulus generation. Solid understanding of digital design concepts, SoC/ASIC design flows, and bus protocols (e.g., AXI, AHB, PCIe, etc.). Hands-on experience with simulation tools (VCS, Questa, etc.) and coverage analysis tools. Excellent debugging and problem-solving skills using waveform viewers and assertion-based techniques. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Strong communication and leadership skills with experience leading small to mid-sized teams. Preferred Qualifications: Experience in formal verification techniques. Experience with emulation, FPGA prototyping, or post-silicon bring-up. Exposure to power-aware or low-power verification (UPF/CPF). Knowledge of hardware security, safety, or compliance standards (ISO 26262, DO-254, etc.) is a plus. Familiarity with CI/CD flows and version control (Git, Jenkins, etc.). Why Join Us: Work on cutting-edge technologies and next-generation chip designs. Opportunity to lead high-impact projects and influence verification strategy. Collaborative and innovative work environment. Competitive salary, benefits, and career growth opportunities.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 3+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals urrently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 8 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education Requirements BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent coursesfrom reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

General Summary: GPU Functional Verification Engineer In the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Description: We are seeking Design Verification Engineers with 515 years of experience in SystemVerilog, UVM, and SoC/IP-level verification. The role involves building scalable verification environments, driving coverage closure, debugging complex issues, and ensuring robust design quality. Key Responsibilities & Requirements: Strong experience in ASIC/IP/SoC design verification (block/IP/SoC level). Expertise in SystemVerilog, UVM, testbench architecture, and reusable verification components. Ability to create and execute detailed verification plans. Skilled in constrained-random verification, functional coverage, assertions, and scoreboarding. Solid knowledge of AMBA protocols (AXI, AHB, APB). Proficiency with simulation tools (VCS, Questa, XSIM, etc.) and debug tools (Verdi, DVE). Strong background in testcase development, coverage closure, and issue debugging. Experience with assertion-based and formal verification techniques. Hands-on in developing block-level and SoC-level verification environments. Scripting skills in Python, Perl, or TCL for automation.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, and more to launch cutting-edge products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with at least 4 years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Some of your responsibilities will include implementing SERDES high-speed Interface PHY designs, RTL development and validation, test-plan development, timing constraints development, DFT insertion, and post-silicon debug support. As a Hardware Engineer at Qualcomm, you are expected to have an MTech/BTech in EE/CS with 8+ years of hardware engineering experience. Your skillset should include micro-architecture development, RTL design, front-end flows, synthesis, DFT, STA, and experience with high-speed interface design and standard protocols like USB/PCIe/MIPI. Post-silicon bring-up and debug experience is considered a plus, along with the ability to collaborate with global teams and possess strong communication skills. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to adhere to all applicable policies and procedures, especially regarding the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies or individuals represented by an agency are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For more information about this role, you can contact Qualcomm Careers.,

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 3 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education Requirements BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent coursesfrom reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Qualcomm India Private Limited is seeking talented engineers for CPU RTL development targeted for high-performance, low-power devices. As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to conceptualize the micro-architecture and contribute to architecture/product definition in the early stages of the product life cycle. Your responsibilities will include performance exploration to devise high-performance strategies with the CPU modeling team, microarchitecture development from early architectural exploration to detailed specification, RTL design ownership to meet power, performance, area, and timing goals, support for functional verification to execute the verification strategy, performance verification to ensure meeting performance goals, and working with a multi-functional engineering team for physical design implementation and validation in terms of timing, area, reliability, testability, and more. Preferred qualifications for this role include a thorough knowledge of microprocessor architecture, expertise in areas such as instruction fetch, decode, branch prediction, instruction scheduling, cache, and memory subsystems, proficiency in Verilog and/or VHDL, understanding of logic design principles, low power microarchitecture techniques, high-performance techniques, and experience with scripting languages like Perl or Python. The minimum qualifications required are a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 6 years of Hardware Engineering experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of relevant experience. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you need accommodations during the application/hiring process, you can email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is solely for individuals seeking employment at Qualcomm, and unsolicited submissions from staffing and recruiting agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

As a Senior Physical Design Engineer with Micron Technology, you will play a crucial role in the HBM Team based in Hyderabad, India. Your primary responsibility will be to design and develop complex Application-Specific Integrated Circuits (ASICs) catering to the requirements and specifications of High Bandwidth Memories (HBM). These memories are utilized in intensive applications like artificial intelligence and high-performance computing solutions, aiming to push the boundaries of technology and innovation. Your role involves designing IPs or Hierarchical blocks solutions for high-performance and low-power applications. You will collaborate closely with cross-functional teams to define project requirements and conduct feasibility studies. Your expertise will be instrumental in creating detailed IPs or Hierarchical blocks design specifications, ensuring alignment with project goals. Additionally, you will enable Place and route, clock tree synthesis capabilities for the System on Chip (SoC) Integration. To excel in this position, you will implement and optimize digital designs using hardware description languages (HDLs) such as Verilog or VHDL, considering various design trade-offs and performance metrics. Your responsibilities will also include evaluating RTL coding, timing analysis, synthesis, and functional verification to ensure the correctness and robustness of the design. As a Senior Physical Design Engineer, you will lead and participate in verification efforts, write testbenches, run simulations, and debug functional and timing issues. Collaboration with physical design engineers is essential to guide and optimize the layout to achieve performance and power targets effectively. Moreover, you will contribute to the evaluation and selection of third-party IP blocks to integrate into the IPs or Hierarchical blocks design. It is crucial to stay updated with the latest design methodologies, tools, and industry trends, continuously enhancing design practices. Additionally, mentoring junior engineers by providing technical guidance and support will be part of your role. To be successful in this position, you should have at least 5 years of relevant work experience focused on RTL to GDS for high-performance architectures. Experience in physical design, timing closure, and physical integration/signoff is essential. You should possess a drive for continuous learning, evaluating microarchitectural options, and interconnecting complex microarchitectural structures and subsystems. Proficiency in hardware description languages (HDLs), familiarity with EDA tools, and a strong understanding of design methodologies are required. Scripting language proficiency for automating design tasks will be advantageous. A Bachelor's degree (BE) or Master's degree (MTech) in Electronic/VLSI Engineering is necessary to qualify for this role. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming the use of information to enrich life for all. If you are passionate about pushing the boundaries of technology and innovation, this role offers an exciting opportunity to contribute to cutting-edge semiconductor products and maintain a competitive edge in the industry.,

Role & responsibilities 4+ Years of experience in Design Verification Expertise in SV & UVM Experience in any one of the following protocols like PCIe, Ethernet, DDR, USB, AXI etc., Excellent Communication

1. 10-15 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).

Qualcomm India Private Limited is looking for talented engineers to join their team for CPU RTL development targeted at high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to conceptualize the micro-architecture and contribute to architecture/product definition in the early stages of the product life-cycle. Your responsibilities will include performance exploration to devise high-performance strategies in collaboration with the CPU modeling team, microarchitecture development and specification from initial architectural exploration to detailed specification, RTL ownership for developing, assessing, and refining RTL design to meet power, performance, area, and timing goals, providing support for functional and performance verification to ensure the design meets the desired goals, and working with a multi-functional engineering team to implement and validate physical design covering aspects like timing, area, reliability, and testability. Preferred qualifications for this role include a deep understanding of microprocessor architecture with expertise in areas such as instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution, integer and floating-point execution, cache and memory subsystems, proficiency in Verilog and/or VHDL, logic design principles, knowledge of low power microarchitecture techniques, familiarity with high-performance techniques, and experience in using scripting languages like Perl or Python. Candidates must possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 6 years of Hardware Engineering or related work experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of experience. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, contact Qualcomm at disability-accommodations@qualcomm.com or through their toll-free number. All employees at Qualcomm are expected to adhere to applicable policies and procedures, including those related to the protection of Company confidential information and proprietary data. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking jobs at Qualcomm, and submissions from agencies will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. For further information about this role, reach out to Qualcomm Careers directly.,

Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulusenhancements and drive improving the debug capabilities for core testbenchenvironments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware * Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 6 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications, processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience - Knowledge of verification principles and coverage.- Knowledge of test generation tools and working with ISA reference model.- Experience with translating ISA specifications to testplan.- Understanding of Agile development processes.- Experience with DevOps design methodologies and tools.

You should be an Electrical, Electronics, or Computer Science Engineer with a very good understanding of Hardware Description Languages (HDLs) such as Verilog and/or VHDL. It is essential to have prior experience in simulation/emulation using these languages. A good working knowledge of Electronic Design Automation (EDA) tools, with a focus on debugging design and verification issues using these tools, is required. Experience in process automation through scripting is also expected. Additionally, familiarity with SystemVerilog, C++, and Universal Verification Methodology (UVM) is highly preferred. Experience in Functional Verification of complex digital systems, such as System on Chip (SoC) Verification, utilizing a Hardware Verification Language (HVL) like SystemVerilog, is crucial. Proficiency in designing and implementing intricate functional verification environments is essential for this role. Moreover, knowledge of protocols like PCIe, USB3/4, and DisplayPort would be advantageous. Join us at Cadence, where we hire and nurture leaders and innovators who are eager to contribute to the ever-evolving world of technology. Let's work together to tackle challenges that others find insurmountable.,

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Multi Clock designs, Asynchronous interface, and Low power SoC design is essential for this role. Your key responsibilities will involve micro-architecture & RTL development, validation for linting, clock-domain crossing, and DFT rules. You will work closely with the functional verification team on test-plan development and waveform debugs at various levels. Experience in constraint development, timing closure, UPF writing, power aware equivalence checks, and low power checks is required. Additionally, you will be supporting performance debugs and addressing performance bottlenecks, along with providing assistance in sub-system, SoC integration, and chip-level debug. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. If you meet the following qualifications and have the required experience, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

We are looking for passionate individuals who are ready to take on challenges in IP/ASIC/SOC Verification. We have open positions at all levels including Engineer, Senior Engineer, Lead, Manager, Director, and Head of Verification. The ideal candidate will have 3-20 years of experience in the field. In this role, you will be an integral part of the ASIC verification team. Your primary responsibility will be the functional verification of ASIC IPs. Our verification methodology utilizes cutting-edge techniques and tools such as coverage-driven constrained random verification and formal verification. Our design and implementation of verification environments heavily rely on object-oriented architectures and frameworks. We are seeking individuals with expertise and aptitude in verifying functions like image processing, video compression, and computer vision. As a verification engineer, you will also get the opportunity to delve into the algorithms that drive the hardware. The ideal candidate is an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. Our verification environments are complex, so a strong ability to comprehend, implement, and maintain intricate software systems is essential. Previous experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods would be advantageous. Analytical thinking, systematic approach, and attention to detail are traits we highly value in potential candidates. If you meet these criteria and are ready for an exciting challenge in the field of ASIC verification, we would love to hear from you. References are most appreciated. (ref:hirist.tech),