81 Functional Verification Jobs - Page 4

The Opportunity Were looking for the Wavemakers of tomorrow. About the job The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll Do Will be responsible for verification of IP, Block, or Subsystem at Soc Level Generate appropriate documentation for verification Responsible for analyzing/debugging given blocks/tasks in verification Should be able to develop and own the verification environment, verification components developed You will report to Lead Engineer What Youll Need: 6+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification Have worked on IP level or Block level or SoC level functional verification Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy Expert in System Verilog, Verilog, and OVM/UVM verification methodology Have working experience on AMBA interface protocols (AXI, AHB, APB) Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must Hands-on experience on working one or more of the following protocols is a must - UART, I2C, SPI, QSPI, I3C, eMMC, CAN, Hands-on experience working with one or more of the following protocols is desired - PCIe, USB, DDR, LPDDR, GBE, SATA Experience with Perl, Python or similar scripting languages will be helpful Ability to adapt & learn, quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Design Verification Engineer (5 to 12 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 5 t o 12 Years Openings: 10 Positions Preferred - Immediate to 45 Days (Notice Period) Job Description : ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Notice Period-Prefer less Notice period or serving. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you"™ll also get to visit other locations in India and globe, so you"™ll need to go where this job takes you. In return, you"™ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE"™s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer"™s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution"™s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don"™t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. #disw #LI-EDA #LI-Hybrid We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow"™s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Siemens Software. Where today meets tomorrow

Exposure to Emulation model build and sanity bring-up Proven Emulation Testbench bring-up experience with C++ and SystemVerilog BFM models Expertise in porting C++/SystemVerilog Simulation Testbenches to Emulation Hands-on experience with SystemVerilog, C++ based testbenches BFM coding using C++ or SystemVerilog Strong Python scripting skills Exposure to GPU emulation model build and sanity bring-up Good understanding of GPU architecture Strong functional verification expertise

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction. We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead: As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy - verification is the key to avoid white spots mixing with stars. We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks. Job role and Skill set - Design role: Senior RTL Subsystems Designer Lead role. With 8+ years of experience. Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s). Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Hands-on experience with low power design. Understanding of DFT requirements and architecture. Working with cross-functional teams and driving the projects to completion. Job role and Skill set - Verification role: Senior Verification lead role. With 8+ years of experience. Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage. Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add. Working with cross-functional teams and driving the projects to completion.