Design and Verification Engineer

Aritrak Technologies

4 - 9 years

4 - 9 Lacs

hyderabad bengaluru

Posted:6 hours ago| Platform:

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Skills Required

design verification soc verification pcie uvm soc ip ovm perl asic axi asic verification amba verilog system verilog ip verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Design Verification Engineer

Key Responsibilities

Perform
block/IP/Sub-System/SoC level design verification
using SV/UVM methodology.
Develop UVM-based
testbenches, sequences, drivers, monitors, and scoreboard
.
Create and execute test plans using
constrained-random and directed testing
.
Drive
functional coverage and code coverage
closure.
Debug simulation failures using tools like
Verdi/SimVision/DVE
.
Work closely with RTL designers and architects to identify and resolve issues.
Manage
regressions
, verification infrastructure, and metrics reporting.
Contribute to verification methodology improvements and automation.

Required Skills

Strong experience in
SystemVerilog & UVM
.
Hands-on experience with
VCS / QuestaSim / Xcelium
simulation tools.
Good understanding of
ASIC/SoC architecture
, clock/reset, and data paths.
Experience with
protocols
such as AXI, AHB, APB, PCIe, USB, DDR, SPI, I2C, etc.
Debugging skills using
waveform tools (Verdi, SimVision, DVE)
.
Familiar with
functional coverage, assertions (SVA)
, and testbench architecture.
Scripting knowledge (Python / Perl / Shell) for automation is preferred.

Good to Have

Experience with
formal verification
.
Knowledge of
UVM RAL
, register model development.
Exposure to
post-silicon validation
.

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