Design and Verification Engineer

4 - 9 years

12 - 24 Lacs

Posted:17 hours ago| Platform: Naukri logo

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Work Mode

Work from Office

Job Type

Full Time

Job Description

Looking for only Bangalore candidates

Responsibilities:

* Develop UVM testbenches using SystemVerilog and ASIC Verification techniques.

* Ensure STA compliance during physical design phase.

Mail: chaitanya.vasamsetti@gigaopsglobal.com

Office cab/shuttleFood allowanceHealth insuranceAnnual bonusProvident fund

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