1.Design Verification Engineer /2. DV- Emulation

5 - 10 years

13 - 19 Lacs

Posted:1 day ago| Platform: Naukri logo

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Skills Required

hands-on with arm-based socs cadence palladium / synopsys zebu / siemens veloce. debuggers tcl system verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role & responsibilities

  • Hands On Experience, in IP/SOC Verification
  • Have Experience of one or more Project Cycles including Tape Outs
  • Design & Verification Failure Debugging Skills
  • Verilog, System Verilog, & UVM Testbench Coding
  • Functional Coverage Development, & Coverage Closure
  • Assertion/Checker Development
  • Testcase Planning & Development
  • Practical Knowledge of Protocols like: PCIe, Ethernet, CXL, USB, CAN,
  • LIN, FlexRay, AXI, AHB, APB
  • Concepts in Digital Design
  • Problem Solving & Analytical Skills

Role & responsibilities

  • Experience with

    Emulation Platforms

    : Cadence

    Palladium

    / Synopsys

    ZeBu

    / Siemens

    Veloce

    .
  • Strong in

    SystemVerilog / UVM

    , acceleration-ready TBs, transactors, and BFMs.
  • Hands-on with

    ARM-based SoCs

    , AMBA (AXI/AHB/APB), cache/memory subsystems.
  • Ability to port simulation TB to emulation and optimize runtime/performance.
  • Exposure to

    C-based testcase development

    for firmware, drivers, or bare-metal validation.
  • Experience in

    HW/SW Co-Verification

    , Linux/bootloader bring-up on emulator.
  • Proficient in

    debug tools

    : Verdi/Indago, waveform debug, logs, and root-cause analysis.
  • Awareness of

    SoC integration

    , clock/power/reset architecture, and peripheral IPs.
  • Strong

    Python/Shell/Perl

    scripting for automation and flow development.

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