Functional Verification Engineer

2 - 5 years

4 - 8 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description


 About The Role  

Project Role :
Functional Verification Engineer

Project Role Description :
Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills :SAP TM Transportation Management

Good to have skills :
NA
Minimum 5 year(s) of experience is required

Educational Qualification :
15 years full time education
Summary:As a Functional Verification Engineer, you will engage in the development and execution of testbenches aimed at verifying the functional correctness of digital designs at both the block and system levels. Your typical day will involve creating constrained-random, directed, and coverage-driven tests using languages such as SystemVerilog and UVM. You will collaborate closely with design and architecture teams to identify corner cases, ensuring that complete functional coverage is achieved prior to tape-out. This role requires a proactive approach to problem-solving and a commitment to maintaining high standards of quality in verification processes.
Roles & Responsibilities:
  • Expected to be an SME.
  • Collaborate and manage the team to perform.
  • Responsible for team decisions.
  • Engage with multiple teams and contribute on key decisions.
  • Provide solutions to problems for their immediate team and across multiple teams.
  • Mentor junior team members to enhance their skills and knowledge in functional verification.
  • Continuously evaluate and improve verification methodologies to ensure efficiency and effectiveness.
    Professional & Technical Skills:
  • Must To Have
    Skills:
  • Proficiency in SAP TM Transportation Management.
  • Strong understanding of digital design verification processes.
  • Experience with SystemVerilog and UVM for testbench development.
  • Ability to create and implement constrained-random and directed tests.
  • Familiarity with coverage-driven verification techniques.
    Additional Information:
  • The candidate should have minimum 5 years of experience in SAP TM Transportation Management.
  • This position is based at our Hyderabad office.
  • A 15 years full time education is required.
     Qualification 15 years full time education
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    Dublin

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