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Functional Verification Engineer

Functional Verification Engineer

Luxoft

3 - 7 years

11 - 15 Lacs

hyderabad

Posted:19 hours ago| Platform:

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Skills Required

soc c uvm verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Project description We are seeking an experienced Functional Verification Engineer with strong expertise in System Verilog/UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently.

Responsibilities

Develop and maintain block-level verification environments and testbenches using SystemVerilog/UVM.

Create and execute verification plans (VPlans), run regressions, and drive coverage closure.

Implement and verify designs using real number modeling (RNM) for mixed-signal interfaces.

Perform netlist and gate-level simulations (GLS) to validate post-synthesis and post-layout functionality.

Debug functional and testbench issues, ensuring high-quality, reusable verification components.

Skills Must have

5-10y exp

Develop and maintain block-level testbenches using System Verilog/UVM.

Create and execute verification plans (Vplan), run regressions, and achieve coverage closure.

Work on testbenches with real number modeling.

Perform netlist and gate-level simulations.

Hands-on coding in SystemVerilog/UVM. Nice to have

Experience with block/IP-level verification; subsystem or SoC-level experience is a plus.

Soft Skills:

Strong communication, ability to work independently and meet schedules.

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Functional Verification Engineer