DFT Implementation: Strong expertise in implementing DFT architectures, including Scan Insertion, ATPG (Automatic Test Pattern Generation), and MBIST/ LBIST for SoC designs. Test Coverage Optimization: Experience in optimizing test coverage while minimizing test cost and pattern volume. Scan & Compression Techniques: Proficient in scan chain design, scan compression techniques, and reducing test data volume. Boundary Scan (IEEE 1149.1): In-depth knowledge of boundary scan standards and Fault Models: Familiarity with various fault models (stuck-at, transition, path delay, etc.) and their application in test generation. DFT Tools: Hands-on experience with DFT tools like Synopsys TetraMAX, Mentor Graphics Tessent, Cadence Modus, etc. Scripting & Automation: Proficiency in scripting languages (e.g., Perl, Python, TCL) for Sign-Off: Experience with DFT sign-off procedures, including coverage analysis, vector generation, and fault simulation. Post-Silicon Validation: Knowledge of silicon bring-up, ATE (Automatic Test Equipment), and post-silicon validation techniques. Expectations from the Role: Technical Expertise: Demonstrated expertise in DFT methodologies, with the ability to implement robust DFT solutions across complex SoC designs. Problem-Solving: Strong analytical and problem-solving skills, particularly in diagnosing and resolving DFT-related issues. Collaboration: Effective communication and teamwork skills, with the ability to work closely with RTL designers, verification teams, and physical design teams. Innovation: Ability to innovate and improve existing DFT methodologies, driving advancements in test coverage and efficiency. Attention to Detail: High attention to detail, ensuring that all test structures are correctly Project Management: Ability to manage multiple projects, prioritize tasks effectively, and ensure timely delivery of high-quality DFT solutions.

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and ECO (Engineering Change Order) for both Process Knowledge: Comprehensive understanding of the entire physical design process from RTL to GDSII, encompassing floorplanning, placement, CTS, routing, and sign-off stages. ECO Implementation: Experience in implementing ECOs. PnR Tools: Hands-on experience with PnR tools such as Synopsys ICC II and Scripting Skills: Proficient in scripting languages like Perl and TCL, with experience using various EDA tools. Expectations from the Role: Debugging & Problem-Solving: Excellent debugging and problem-solving skills, with the ability to tackle complex design issues. Communication: Effective communication skills for interacting with all Focus & Commitment: Must be highly focused and committed to achieving project goals and closing out tasks. Independence: Ability to work independently and manage tasks with minimal Leadership: Possesses strong leadership skills with a proactive, go-getter attitude.

Digital Logic Design: Strong expertise in digital logic design with hands-on experience in RTL coding using Verilog and SystemVerilog. Peripheral Design: Experience in designing high-speed and low-speed peripherals. Design Optimization: Understanding of synthesis, timing constraints, clock domain crossing (CDC), and logic optimization techniques. Low Power Design: Exposure to low power design techniques, including working with multiple power and clock domains will be advantage. Protocol Knowledge: knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, and SPI will be preferred. Expectations from the Role: Communication & Independence: Excellent communication and interpersonal skills, with the ability to work independently. Adaptability: A fast learner who can efficiently operate in a distributed work Initiative & Punctuality: Demonstrates ownership, initiative, and punctuality in all

ARF Design Pvt Ltd is looking for Physical Design Engineer/Lead to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skillsStrong analytical and problem-solving skillsFamiliarity with scripting languages, such as Tcl, Perl, or Python

Job Title: Analog Design Engineer / Lead Location: Location: Bengaluru/Bhubaneswar/Ranchi Experience: 5 - 10 Years Technical Requirements: Analog Circuit Design: Strong expertise in designing and simulating analog circuits such as amplifiers, ADCs/DACs, voltage regulators, PLLs, and other mixed-signal Tools & Methodologies: Proficient in using EDA tools for schematic capture, circuit simulation (e.g., SPICE), layout, and post-layout verification. Layout Techniques: Deep understanding of analog layout techniques, including matching, noise reduction, and parasitic minimization. Design for Performance: Experience in optimizing designs for low power, high speed, and area efficiency. Process Knowledge: Familiarity with CMOS process technology, including the impact of process variations on analog performance. Verification & Validation: Skilled in analog/mixed-signal verification methodologies, including behavioral modeling and corner case analysis. Tape-Out Experience: Experience with silicon validation and characterization, including working through tape-out processes. Expectations from the Role: Problem-Solving: Strong analytical and problem-solving skills, with the ability to troubleshoot complex circuit issues. Collaboration: Effective communication and teamwork skills, with the ability to collaborate with digital and layout teams. Attention to Detail: High attention to detail to ensure design accuracy and Innovation: Ability to innovate and optimize designs within the constraints of the Project Management: Ability to manage multiple tasks and projects, ensuring timely

Digital Logic Design: Strong expertise in digital logic design with hands-on experience in RTL coding using Verilog and SystemVerilog. Peripheral Design: Experience in designing high-speed and low-speed peripherals. Design Optimization: Deep understanding of synthesis, timing constraints, clock domain crossing (CDC), and logic optimization techniques. Automation: Proven experience in automating RTL generation for various design Low Power Design: Exposure to low power design techniques, including working with multiple power and clock domains. SoC Integration: Familiarity with ARM SoC, AMBA IP-based designs, and SoC/sub- Protocol Knowledge: Strong knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, and SPI is highly desired. Expectations from the Role: Communication & Independence: Excellent communication and interpersonal skills, with the ability to work independently. Adaptability: A fast learner who can efficiently operate in a distributed work Initiative & Punctuality: Demonstrates ownership, initiative, and punctuality in all responsibilities. Leadership: Ability to mentor and lead a team to solve complex design challenges.

RF Circuit Design: Expertise in the design and simulation of RF circuits such as LNAs, mixers, power amplifiers, VCOs, and filters. Tools & Simulation: Proficient in using RF design tools (e.g., ADS, HFSS, Cadence Virtuoso) and simulation methodologies for RF circuits. Layout Considerations: Strong understanding of RF layout techniques, including impedance matching, parasitic extraction, and electromagnetic interference (EMI) Antenna Design: Experience in antenna design and integration within RF systems. System Integration: Knowledge of RF system architecture, including transceiver design and RF signal chain analysis. Test & Measurement: Skilled in using RF test equipment (e.g., spectrum analyzers, network analyzers) for design validation and characterization. Regulatory Compliance: Familiarity with RF compliance standards and regulatory requirements (e.g., FCC, ETSI). Expectations from the Role: Technical Expertise: Strong technical expertise in RF design principles and the ability to innovate within challenging design constraints. Collaboration: Excellent communication and collaboration skills, with the ability to work closely with cross-functional teams. Problem-Solving: Ability to diagnose and resolve complex RF issues through both simulation and lab measurements. Time Management: Ability to manage multiple projects simultaneously, ensuring timely delivery of high-quality designs. Leadership: Potential to lead and mentor junior engineers within the team.

Memory Architecture: In-depth knowledge of memory design architectures, including SRAM, DRAM, Flash, and other non-volatile memory types. Circuit Design: Expertise in designing memory cells, sense amplifiers, decoders, and other associated memory circuit blocks. Process Technology: Familiarity with advanced CMOS technology nodes and their impact on memory design, including scaling challenges. Design Optimization: Experience in optimizing memory for performance, power, and area, including techniques for reducing leakage and improving access times. Verification & Validation: Proficient in memory verification techniques, including corner analysis, reliability testing, and post-silicon validation. EDA Tools: Hands-on experience with memory design tools, including Cadence, Synopsys, and Mentor Graphics. Yield Enhancement: Knowledge of yield enhancement techniques, including redundancy and error correction codes (ECC). Expectations from the Role: Technical Leadership: Strong technical leadership skills with the ability to guide and mentor junior team members. Problem-Solving: Excellent problem-solving abilities, particularly in diagnosing and resolving memory design challenges. Innovation: Ability to innovate and drive improvements in memory design, balancing performance and manufacturability. Collaboration: Strong communication and teamwork skills, with the ability to work effectively with cross-functional teams. Project Focus: Ability to manage and prioritize multiple projects, ensuring timely