DFT Implementation: Strong expertise in implementing DFT architectures, including Scan Insertion, ATPG (Automatic Test Pattern Generation), and MBIST/ LBIST for SoC designs. Test Coverage Optimization: Experience in optimizing test coverage while minimizing test cost and pattern volume. Scan & Compression Techniques: Proficient in scan chain design, scan compression techniques, and reducing test data volume. Boundary Scan (IEEE 1149.1): In-depth knowledge of boundary scan standards and Fault Models: Familiarity with various fault models (stuck-at, transition, path delay, etc.) and their application in test generation. DFT Tools: Hands-on experience with DFT tools like Synopsys TetraMAX, Mentor Graphics Tessent, Cadence Modus, etc. Scripting & Automation: Proficiency in scripting languages (e.g., Perl, Python, TCL) for Sign-Off: Experience with DFT sign-off procedures, including coverage analysis, vector generation, and fault simulation. Post-Silicon Validation: Knowledge of silicon bring-up, ATE (Automatic Test Equipment), and post-silicon validation techniques. Expectations from the Role: Technical Expertise: Demonstrated expertise in DFT methodologies, with the ability to implement robust DFT solutions across complex SoC designs. Problem-Solving: Strong analytical and problem-solving skills, particularly in diagnosing and resolving DFT-related issues. Collaboration: Effective communication and teamwork skills, with the ability to work closely with RTL designers, verification teams, and physical design teams. Innovation: Ability to innovate and improve existing DFT methodologies, driving advancements in test coverage and efficiency. Attention to Detail: High attention to detail, ensuring that all test structures are correctly Project Management: Ability to manage multiple projects, prioritize tasks effectively, and ensure timely delivery of high-quality DFT solutions.