Functional Verification Engineer

Role Overview: As a Functional Verification Engineer, you will engage in the development and execution of testbenches aimed at verifying the functional correctness of digital designs at both the block and system levels. Your typical day will involve creating constrained-random, directed, and coverage-driven tests using languages such as SystemVerilog and UVM. You will collaborate closely with design and architecture teams to identify corner cases, ensuring that complete functional coverage is achieved prior to tape-out. This role requires a proactive approach to problem-solving and a commitment to maintaining high standards of quality in verification processes. Key Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisions. - Engage with multiple teams and contribute on key decisions. - Provide solutions to problems for their immediate team and across multiple teams. - Mentor junior team members to enhance their skills and knowledge in functional verification. - Continuously evaluate and improve verification methodologies to ensure efficiency and effectiveness. Qualifications Required: - Must To Have Skills: Proficiency in SAP TM Transportation Management. - Strong understanding of digital design verification processes. - Experience with SystemVerilog and UVM for testbench development. - Ability to create and implement constrained-random and directed tests. - Familiarity with coverage-driven verification techniques. (Note: Additional details of the company are not provided in the Job Description),