Functional Verification Engineer

Lead Functional Verification Engineer

Experience

Location

• Lead verification activities for complex CPU cores, memory subsystems, and high-speed PCIe IPs.
• Define verification strategy, test plan, and coverage goals based on architecture and spec reviews.
• Build and maintain advanced UVM-based testbenches for block and subsystem-level verification.
• Develop reusable components like drivers, monitors, and scoreboards tailored for CPU/memory/PCIe protocols.
• Drive constrained-random and directed test development to validate corner cases and protocol compliance.
• Perform end-to-end data path and coherency checks across memory hierarchies and interfaces.
• Debug RTL and testbench issues using tools like Verdi, SimVision, and waveform viewers.
• Ensure functional and code coverage closure with justification for uncovered items.
• Integrate formal assertions and collaborate with formal teams for protocol and control logic validation.
• Validate compliance with PCIe protocol using checkers and compliance test suites.
• Review and provide feedback on architecture, micro-architecture, and design specifications.
• Automate regressions, triage failures, and provide regular reports using Python/Perl scripting.
• Collaborate closely with architecture, design, DFT, and post-silicon validation teams.
• Mentor junior verification engineers and contribute to methodology improvements.
• Document verification results, sign-off criteria, and participate in design milestone reviews.

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.