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Functional Verification Engineer

Functional Verification Engineer

ACL Digital

4 years

0 Lacs

Bengaluru Karnataka India

Posted:1 day ago| Platform:

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Skills Required

verification ip test design systemverilog analysis code simulation architecture analyze verilog scripting perl python debugging usb

Work Mode

On-site

Job Type

Full Time

Job Description

Job Title:

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Functional Verification Engineer

Key Responsibilities:

Develop and execute verification test plans based on design specifications and architecture.
Design and implement testbenches using SystemVerilog and UVM methodology.
Create constrained-random and directed test cases.
Build verification components (agents, monitors, scoreboards, checkers).
Perform coverage analysis (code and functional) and close coverage gaps.
Debug simulation failures and work closely with design and architecture teams.
Conduct regressions and analyze results for functional and performance issues.
Document test plans, verification environments, and test results.
Participate in design and verification reviews.

Required Skills:

4+ years of hands-on experience in
functional verification
of IP/SoC.
Strong knowledge and working experience with
SystemVerilog and UVM
.
Familiarity with RTL design (Verilog/VHDL).
Experience in coverage-driven verification, assertions, and functional coverage closure.
Proficient in using simulators like VCS, Questa, or Incisive.
Good scripting skills in
Perl, Python, or Shell
for automation.
Strong debugging skills using simulation waveform viewers.
Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc

Interested can Share CV to sharmila.b@acldigital.com

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