Design, and verify FPGA Zynq ORAN for high-speed. IFFT/FFT blocks and digital filters JESD204B interfaces for high-speed RF transceivers or SoCs. Develop and integrate high-speed Ethernet IP cores (10G/25G/40G) within FPGA-based systems.
+ 3-9 years of experience working on custom FPGA boards and / or FPGA Prototyping platform such as Cadence Protium, Zebu HAPS, etc + In depth experience with FPGA concepts and implementation - debug, performance and throughput tuning, Perform FPGA Synthesis, Place & Route, timing optimizations. You should have knowledge about the FPGA flow from RTL to Bitstream generation. + Perform bring-up, debug, and validation of designs to achieve functional and performance goals + Experience with Verilog / System Verilog RTL and comfortable understanding the RTL code + Experience developing scripts using Python, Perl and Makefile. + You should be passionate about Computer Architecture ARM knowledge on AMBA Bus, USB, + Ethernet, PCIe, MiPI , DDR etc protocols is a plus work towards enabling verification of the next generation SOC on FPGA hardware platform. to envision, develop and deploy new capabilities to accelerate bug finding in pre-silicon . + Develop the infrastructure, flows and methodologies to make this effort scalable and sustainable long term. + Resolve synthesis issues, do capacity and performance tuning and address timings issues. + Help debug functional failures during bringup and execution on the FPGA using off-shelf debuggers, + FPGA debug capabilities, etc. Role & responsibilities
Responsibilities: + DFT (Scan, MBIST, ATPG, Boundary Scan), + Experience leading DFT activities at IP and chip level