Work from Office
Full Time
Scan insertion & ATPG using Fastscan/TestKompress /DFTCompiler/DFTMax/DFTAdvisor/TetraMax.
Pattern Simulation with and without timing annotation & debugging simulation mismatches (VCS/Modelsim/NCSim).
* Familiarity with WGL/TDL file formats.
* Scan compression techniques/LogicBIST.
* Exposure to Memory BIST insertion tools (preferably LogicVision MBIST/Mentor MBISTArchitect).
* Boundary Scan, JTAG concepts, Core testing using P1500.
* Basic understanding of Tester requirements, basics of synthesis and timing. Knowledge of formal verification. Exposure to SoC level DFT.
Mirafra
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