Design Testability Engineer

ti Steps

0 - 5 years

3 - 7 Lacs

hyderabad chennai bengaluru

Posted:3 days ago| Platform:

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Skills Required

jtag dft bist boundary scan mbist scan insertion dft architecture asic atpg rtl

Work Mode

Work from Office

Job Type

Full Time

Job Description

About the Role:

Design Testability Engineer (DFT Engineer)

Key Responsibilities:

Develop and implement
DFT architecture and methodologies
for ASIC/SoC designs.
Design and integrate
scan chains, boundary scan (JTAG), MBIST, and LBIST
into digital designs.
Collaborate with RTL design, synthesis, and physical design teams to ensure
testability requirements
are met.
Perform
test coverage analysis
and optimize DFT insertion to achieve desired coverage metrics.
Generate and validate
test patterns
using ATPG (Automatic Test Pattern Generation) tools.
Work on
silicon bring-up, validation, and failure analysis
during post-silicon testing.
Support
ATE (Automated Test Equipment)
pattern generation, simulation, and debugging.
Participate in
DFT verification
to ensure correct scan insertion, compression, and pattern simulation.
Analyze test results and debug DFT-related issues at chip and board levels.

Preferred Skills :

Experience with
scan compression
,
boundary scan insertion
, or
test point insertion techniques
.
Knowledge of
low-power DFT strategies
(for multi-voltage and multi-domain designs).
Familiarity with
DFM (Design for Manufacturability)
and
yield improvement techniques
.
Experience in
post-silicon validation
and
ATE environments (Advantest, Teradyne, etc.)
.

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