Design Testability Engineer

ti Steps

1 - 4 years

2 - 6 Lacs

hyderabad chennai bengaluru

Posted:4 weeks ago| Platform:

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Skills Required

dft architecture asic dft rtl mbist scan insertion jtag atpg bist boundary scan

Work Mode

Work from Office

Job Type

Full Time

Job Description

About the Role:

Design for Testability (DFT) Engineer

Key Responsibilities:

Collaborate with
design and verification teams
to integrate test features into ASIC, FPGA, or PCB designs.
Develop and implement
DFT strategies
including scan insertion, boundary scan, built-in self-test (BIST), and other test methodologies.
Create
test plans, scripts, and models
for pre-silicon and post-silicon validation.
Conduct
design reviews
to ensure testability and adherence to DFT best practices.
Analyze
fault coverage and test data
to identify design improvements.
Collaborate with manufacturing teams to support
production test development and failure analysis
.
Develop and maintain
DFT documentation, guidelines, and reports
.
Stay updated with emerging
DFT tools, techniques, and industry standards
.

Required Skills & Qualifications:

Bachelors or Master’s degree
in Electronics, Electrical Engineering, Computer Engineering, or related field.
3–7+ years
of experience in
DFT, verification, or design engineering
.
Strong knowledge of
test methodologies
: scan, BIST, boundary scan, and ATPG.
Experience with
EDA tools
such as Synopsys, Cadence, Mentor Graphics, or similar for DFT implementation.
Proficiency in
HDL languages
(Verilog, VHDL, SystemVerilog).
Familiarity with
ASIC/FPGA design flow
and verification processes.

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