70 Dft Architecture Jobs

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Role Summary: As a DFT engineer at Alphawave Semi,...

DFT architecture, ATPG, MBIST, BIST, Memory Test, RTL, DFT rule check, gate level simulations, Scan Insertion, Scan Chain, Test Coverage Analysis,STA Contact- gagan@bestnanotech.in

Eximietas Design is expanding its team and we are currently looking for DFT Engineers to join us at our Bangalore and Ahmedabad locations. If you have 5+ years of experience in DFT (ASIC/SoC) , this could be a great opportunity for you. Role: DFT Engineer Experience: 5+ years Locations: Bangalore / Ahmedabad Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs Scan insertion, ATPG, scan stitching, MBIST/Logic BIST implementation Boundary scan (IEEE 1149.1), JTAG implementation & validation Test pattern creation & validation (stuck-at, transition, path delay faults) Collaborate with RTL, synthesis, and physical design teams to ensure DFT complian...

Position: DFT Engineers Experience: 5+ relevant experience. Location - India To Be Successful In This Role You Will Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools . Technical Skillset Required Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor tools Like Tetramax, Modus ,Tessent and DC tools Hands on in ATPG, SCAN and MBIST insertion and simulation Knowledge on JTAG is an added advantage . Good Simulation debugging skills Technical Docum...

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. You will be responsible for various key tasks including: - Scan architecture planning - Pin mixing - Scan compression planning and optimization for pattern volume for SA and TD pattern sets - Scan synthesis - Power optimization techniques in test modes - MBIST architecture planning, repair architectures, insertion, verification - Analog and mixed signal IP testing architecture and verification You will also be involved in: - Timing closure of scan, MBIST, and other test modes ...

As a Lead Hardware Engineer - DFT IP R&D at Cadence Design Systems, you will have the opportunity to work on cutting-edge technologies within the MODUS DFT software solution. You will be a vital part of the R&D team, contributing to the development of innovative technologies that drive technology leadership in the DFT space. Your role will involve designing, developing, troubleshooting, debugging, and supporting the MODUS software product. **Key Responsibilities:** - Design and verify Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features such as full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at both block and SoC levels. - Provide R&D su...

Mirafra Technologies hiring DFT_Engineers for Multiple Projects: Experience - 4+ year onwards Notice period - 0 to 30 days Location - Bangalore Apply at sayantikamajumdar@mirafra.com Call / Whatsapp: +91 - 9007115796 JD 1: 1. MBIST , scan insertion, DRC analysis and DRC resolving , ATPG and simulations for Asics. 2. Test coverage improvement and Hierarchial test knowledge 3. Good debugging skills 4. Hands-on experience with Synopsys tools - TestMax Manager/ TestMax Atpg/ TestMax Advisor/VCS 5. knowledge on PD/Timing collaterals. JD 2: Worked on ATPG , GLS (No Timing & Timings). exp in Python based Script for ATPG , GLS & Post Si Diagnosis flows. JD 3: DFT Tools flow: Mentor Tessent Implement...

Were Hiring: Senior DFT Engineer Location: Bangalore, India Experience: 8+ Years Key Responsibilities: Define and implement IC-level DFT architecture Expertise in JTAG , scan insertion , compression , ATPG , and boundary scan Perform timing & no-timing simulations Implement Memory BIST (RAM & ROM) Collaborate effectively and work independently Requirements: Strong knowledge of DFT methodologies Excellent communication skills (written & verbal) Experience with Memory BIST repair flow (plus) Post-silicon debug experience (plus) Familiarity with Verilog/VHDL , Synthesis , STA , LEC (plus) Experience with Ultra Low Power Designs , Conformal Low Power (plus) Analog DFT experience (plus) Apply Now...

Industry: VLSI Function: Design for Testability ATPG, MBIST, Tessent, Boundary scan, eFuse, JTAG, LBIST, scan chain, TAP controller IEEE 1149.1/1838/1500/1687.x, UDFM, Cell-Aware, Layout Aware, Python SCAN DFT, ATPG, Diagnostic, Coverage Analysis

Role: DFT Engineer Experience:6+ years Location: Bangalore Salary: Can be discussed Job Description We are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to, working on various aspects of IP and SoC DFT including the DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan and ATPG. SCAN insertion, ATPG and pattern simulation/debug. MBIST and Repair implementation and verification TOP DFT architecture Design ATE vector setup and Yield improvement The candidate must be able to drive the DFT implement...

We are looking for Senior DFT-MBIST Engineer with 5+Yrs of relevent experience in DFT Design Responsibilities Implement/Integrate and verify DFT logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns Participate in post-silicon activity like bring up, diagnostics and characterization Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams. Scan insertion, Scan compression, Stuck-At, At-Speed test and cov...

About the Role: We are seeking a skilled Design for Testability (DFT) Engineer to work closely with the design and verification teams to ensure that hardware designs are testable and meet quality standards. The ideal candidate will have experience in incorporating test structures into designs, creating test plans, and developing automated test strategies to identify manufacturing defects and ensure product reliability. Key Responsibilities: Collaborate with design and verification teams to integrate test features into ASIC, FPGA, or PCB designs. Develop and implement DFT strategies including scan insertion, boundary scan, built-in self-test (BIST), and other test methodologies. Create test p...

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate...

Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must. Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation. A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers

We’re hiring a skilled DFT Engineer with 6–9 years of experience in ATPG, Scan Insertion, and DFT Architecture. The ideal candidate will have strong debugging, scripting, and STA/timing closure expertise for VLSI front-end design. Required Candidate profile Experienced DFT Engineer with hands-on exposure to ATPG,Scan Insertion, and Static Timing Analysis. Strong in debugging,scripting (Perl/Python/TCL),and collaboration within global semiconductor teams.

Position: Senior DFT Engineer Location: Bangalore / Hyderabad Experience: 5+ Years Email: karthik.adasu@proxelera.com Job Description: We are seeking an experienced Senior DFT Engineer with strong expertise in DFT design, verification, and test methodologies. Key Responsibilities: * Implement and verify DFT logic including MBIST, scan chains, compression, TAP, iJTAG, and eFuse. * Perform scan insertion, scan compression, ATPG pattern generation, and coverage analysis. * Execute MBIST insertion, simulation, and debug at RTL and gate levels. * Collaborate with silicon and test engineering teams for test plan creation and pattern generation. * Participate in post-silicon bring-up, diagnostics, ...

We’re hiring a DFT Lead with 10+ years of experience in VLSI front-end design. The role involves DFT architecture, ATPG, scan insertion, STA, timing closure, and debug. Strong scripting and communication skills are essential. Required Candidate profile Experienced DFT professional skilled in ATPG, scan insertion, and timing closure. Proven ability to lead design-for-test implementation and debugging in complex SoC environments using industry tools.

Principal Member Technical Staff About The Role Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, d...

About the Role: We are seeking a skilled and detail-oriented Design Testability Engineer (DFT Engineer) to join our hardware design team. The ideal candidate will be responsible for developing and implementing Design for Test (DFT) strategies for complex SoCs, ASICs, or IC designs to ensure high-quality and efficient silicon testing and validation. Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs. Design and integrate scan chains, boundary scan (JTAG), MBIST, and LBIST into digital designs. Collaborate with RTL design, synthesis, and physical design teams to ensure testability requirements are met. Perform test coverage analysis and optimize...

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, ...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

Alternate Job Titles: Senior RTL Design Lead We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished RTL design expert with a proven track record in leading complex ASIC digital subsystems from concept to silicon. Thriving on technical challenges, you find deep satisfaction in delivering first-time...

Role & responsibilities We are looking for a DFT Engineer to join our team in Bangalore, Whitefield.4 This is a permanent opportunity where you'll be a key contributor to our projects. The ideal candidate demonstrates excellent technical knowledge, strong communication skills, and an awareness of project management issues. You should be able to keep your composure during crises, handle risks and uncertainty, and have a strong desire to learn and explore new technologies. This role requires good analysis and problem-solving skills, and the ability to exercise independent judgment in selecting methods and techniques to find solutions. You will contribute to complex aspects of projects, develop...

General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and...

Eximietas Design is expanding its team and we are currently looking for DFT Engineers to join us at our Bangalore, Ahmedabad, Pune and Hyderabad locations. If you have 5+ years of experience in DFT (ASIC/SoC) , this could be a great opportunity for you. Role: DFT Engineer Experience: 5+ years Locations: Bangalore, Ahmedabad, Pune and Hyderabad Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs Scan insertion, ATPG, scan stitching, MBIST/Logic BIST implementation Boundary scan (IEEE 1149.1), JTAG implementation & validation Test pattern creation & validation (stuck-at, transition, path delay faults) Collaborate with RTL, synthesis, and physical...