DFT Engineer

Meyvnsystems

4 - 9 years

7 - 17 Lacs

hyderabad bengaluru

Posted:1 day ago| Platform:

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Skills Required

jtag atpg mbist scan insertion dft architecture compression dft scanning bist boundary scan memory bist tetramax

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role & responsibilities

4-9 years of complete hands-on experience in - DFT Architecture, Design, Scan, MBIST, Gate Level simulations with Timing, DFT Constraints, Pattern Generation, and ATE support.
Should be familiar with SoC & IP level DFT Architecture and Flows from RTL to production.
Able to understand and implement requirements from Test engineering perspective
Familiarity with either Synopsys or Tessent Scan flows.
Simulation tools: NCSIM/XCELIUM/VCS
Should have handled aspects of Scan Scan Insertion, ATPG, Coverage improvement, Pattern Generation on their own. Familiarity with various test pattern formats – STIL, WGL, VEC formats.
Experienced in defining DFT constraints, Timing Closure in DFT modes and handling Gate level simulations with timing at various corners.
Able to implement ECO flows to resolve issues observed at NETLIST level.
Experienced in MBIST flows – Insertion, Simulation and Pattern generation.
The ability to deal with Mixed-Signal design test controllability and observability can be a major plus.
Should be able to support ATE and HTOL teams for post-silicon debug support.
Experience in Tcl/Tk, PERL, Makefile is a Plus
Technologies
: 28nm andbelow.

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