Sr. Design Verification Engineer

Meyvnsystems

6 - 11 years

19 - 34 Lacs

Hyderabad Bengaluru Malaysia

Posted:1 month ago| Platform:

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Skills Required

PCIE SOC Verification UVM Apb Ddr Axi ASIC Verification Amba Ethernet Rtl Verification Ahb System Verilog Ip Verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Responsibilities

6 to 12 years of complete hands-on experience in RTL Verification at both SoC/IP level.
Should be proficient in building New or maintain existing SV/UVM/C based testbenches.
Experienced in SV-UVM/OVM/VMM Methodologies. Specman hands-on can be a plus.
Should have handled Complex Blocks/Hard Macro Level Functional Verification at both RTL and Gate Level.
Should have experience dealing with Coverage Models and metrics issue and closure based on specification.
Able to develop and track Test Plan & Validation Plans based on Specification. Able to setup Regression environments based on Test Plans.
Experience in dealing GPIO, Clock Controller, DFTMUX, System controller such as PMU/CMU/TMU and power issues at SoC level will be an advantage.
Knowledge on Power-Aware -CPF/UPF Simulation at both RTL and Timing Simulations at Gate Level.
Able to Work closely with the Architecture, Design, Synthesis and Physical Design team teams to resolve the RTL/GLS level issues.
Should have knowledge on any of the Bus interface - PCIe/USB/I2C/SPI/UART.
Should have worked on AMBS protocols.
Technologies: 28nm and below.
Experience in Tcl/Tk, PERL, Makefile is a definite Plus.

Qualifications

Education: B.Tech/BE/ME/M.Tech

More Jobs at Meyvnsystems

Sr. Design Verification Engineer

Hyderabad, Bengaluru, Malaysia

6.0 - 11.0 yrs

INR 19 - 34 Lacs

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