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Samsung Electronics
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Design Engineer

Design Engineer

Samsung Electronics

5 - 9 years

0 Lacs

karnataka

Posted:1 month ago| Platform: Shine logo

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Skills Required

implementation timing closure verification rtl physical design dft architecture postsilicon validation scan architecture planning pin mixing scan compression planning optimization for pattern volume sa td pattern sets scan synthesis power optimization techniques mbist architecture planning repair architectures insertion analog mixed signal ip testing architecture jtag operation ijtag protocol functional test cases io testing testing of arm processor cores

Work Mode

On-site

Job Type

Full Time

Job Description

As a Senior DFT Engineer at Samsung Semiconductor India Research (SSIR), you will play a crucial role in full chip DFT architecture, implementation, timing closure, and post-silicon validation. Your responsibilities will include: - Planning scan architecture and optimization for pattern volume - Performing pin mixing and scan compression planning - Implementing power optimization techniques in test modes - Planning MBIST architecture and insertion - Verifying analog and mixed signal IP testing architecture You will also be responsible for tasks such as timing closure of scan and MBIST, writing SDCs, debugging timing issues, and interpreting tester results. Additionally, you will need to understand JTAG operation, iJTAG protocol, functional test cases, IO testing, and ARM processor cores testing. Qualifications required for this role include a Bachelor's or Master's degree in Engineering with a minimum of 5 years of relevant experience. It is essential to demonstrate leadership skills, effective team interaction, risk anticipation, and project planning abilities. Samsung Semiconductor India Research (SSIR) is committed to diversity and Equal Employment Opportunity for all individuals, regardless of their characteristics protected by law.,

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Design Engineer