3 Postsilicon Validation Jobs

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Principal Systems Debug Lead THE ROLE: Technical leader responsible for System and Silicon Debug of AMD EPYC Server products. The successful candidate will work as part of the post-silicon validation group; facilitating all aspects of debug and resolution for system level failures working with engineering teams across AMD. Candidate will be immersed in challenging work developing & executing debug strategy for optimal debug throughput on current product to meet project milestones at POR quality. The system debug lead will also help in driving improvements to current product and future debug methodology. The candidate should be able to work in a global environment while maintaining a synergetic culture. The Person As a key contributor to the success of AMDs product, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry leading technologies to market. As System Debug Lead you will be responsible for post-Silicon debug in the next generation of AMDs flagship server CPU products. In this role you will facilitate the debug efforts of a program to ensure the maximum debug throughput is achieved. The System debug lead will also help to drive improvements in the current product and future debug methodology working withSystem Validation and Engineering teams and other stakeholders (System Architects, IP design, SoC, FW, SW, manufacturing). Key Responsibilities Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills 15+years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such asPCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack. Academic Credentials Bachelors/Masters in Computer Engineering with 15+ years of applicable experience. Location: Bangalore, India Benefits offered are described: AMD benefits at a glance. ,

Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. Check out our CEO talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class solutions for the data center. Ventana is well-funded and backed by some of the largest strategic investors in the industry with the goal of building best-in-class CPU cores for cloud, enterprise, 5G, and Edge computing. We invite you to join the revolution and contribute to one of the Hottest Semiconductor startups in the industry. CPU Micro Architect /Logic Designer Responsibilities: Develop and refine microarchitecture, write design specifications, and deliver and maintain RTL for CPU Core and/or system-level sub-units Work with physical design engineers to physically realize Core/subsystem RTL using deep sub-micron process technologies Work with design verification/validation engineers to effectively test and debug Core/subsystem-level RTL in simulation, prototyping platforms, and silicon Help model, analyze, debug, and address performance issues and opportunities Qualifications Required: 8+ years industry experience working on RTL for high performance CPU or GPU, memory subsystem, or related system-level designs Bachelors or Masters degree in related engineering field Ability to work independently and across geographies Strong domain knowledge of computer architecture Skills Desired: Verilog/SystemVerilog development experience Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems Experience with high frequency design considerations (timing, power, multiple clock domains, etc.) Experience with typical front-end tools including: Verilog simulators, waveform viewers, and linting tools, as well as logic synthesis and place and route Experience in compiled and/or interpreted (Python, perl) languages Unit or feature ownership throughout the project lifecycle Post-silicon validation Bachelors or Masters degree in computer science or related engineering fields EEOE COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidates services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventanas CFO. Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.,

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think were "old" (36 years strong) and only about hardware, but were also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you cant put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair Dont care. Tattoos Show off your ink. Like polka dots Thats cool. Pop culture geek Many of us are. Passion for technology and world changing Be you, with us!,