5.0 - 9.0 years

0 Lacs

karnataka

On-site

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. You will be responsible for various key tasks including: - Scan architecture planning - Pin mixing - Scan compression planning and optimization for pattern volume for SA and TD pattern sets - Scan synthesis - Power optimization techniques in test modes - MBIST architecture planning, repair architectures, insertion, verification - Analog and mixed signal IP testing architecture and verification You will also be involved in: - Timing closure of scan, MBIST, and other test modes ...

Posted 1 week ago

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Senior Design Verification Engineer ACL Digital

4.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. Should be an enthusiastic and a quick learner of the verification flow. Job Description: SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Experience with python or any other scripting language is a plus Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Experience: 4 to 6 Years Location: Hyderabad

Posted 2 months ago

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Design Engineer Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a Senior DFT Engineer at Samsung Semiconductor India Research (SSIR), you will play a crucial role in full chip DFT architecture, implementation, timing closure, and post-silicon validation. Your responsibilities will include: - Planning scan architecture and optimization for pattern volume - Performing pin mixing and scan compression planning - Implementing power optimization techniques in test modes - Planning MBIST architecture and insertion - Verifying analog and mixed signal IP testing architecture You will also be responsible for tasks such as timing closure of scan and MBIST, writing SDCs, debugging timing issues, and interpreting tester results. Additionally, you will need to unde...

Posted 2 months ago

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Design Engineer Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. As part of the team, you will be responsible for various key tasks including scan architecture planning, pin mixing, scan compression planning, and optimization for pattern volume for SA and TD pattern sets. Your expertise will be crucial in scan synthesis, power optimization techniques in test modes, MBIST architecture planning, repair architectures, insertion, verification, and analog and mixed signal IP testing architecture and verification. In this role, you will also be i...

Posted 5 months ago

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