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Design Engineer Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a Senior DFT Engineer at Samsung Semiconductor India Research (SSIR), you will play a crucial role in full chip DFT architecture, implementation, timing closure, and post-silicon validation. Your responsibilities will include: - Planning scan architecture and optimization for pattern volume - Performing pin mixing and scan compression planning - Implementing power optimization techniques in test modes - Planning MBIST architecture and insertion - Verifying analog and mixed signal IP testing architecture You will also be responsible for tasks such as timing closure of scan and MBIST, writing SDCs, debugging timing issues, and interpreting tester results. Additionally, you will need to unde...

Posted 1 month ago

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