Senior DFT-MBIST Engineer

4 - 9 years

25 - 40 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

We are looking for Senior DFT-MBIST Engineer with 5+Yrs of relevent experience in DFT Design

Responsibilities

  • Implement/Integrate and verify DFT logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips.
  • Work with silicon engineering team to create test plans and generate test patterns
  • Participate in post-silicon activity like bring up, diagnostics and characterization
  • Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.
  • Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis
  • MBIST insertion, simulation and debug on RTL and gates netlist
  • Scan ATPG pattern generation, simulation and debug on RTL and gates netlist
  • In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
  • Integrate DFT/BIST insertion flows into synthesis flow

Must-have qualifications:

  • Minimum 5 years of industry experience
  • Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor DFT Tools, Synopsys Simulation Tools)
  • Experience with RTL design and Design verification principles
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
  • Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl
  • Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
  • Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations
  • Ability to communicate and work with multi-disciplined teams across multiple sites and time time zones.

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