Lead Hardware Engineer - DFT IP R&D

As a Lead Hardware Engineer in the DFT IP R&D team at Cadence Design Systems, you will be responsible for working on the MODUS DFT software solution. This comprehensive product aims to achieve high coverage, reduce test time, and provide superior PPA. Your expertise in areas such as RTL design, DFT architecture, verification, power analysis, and optimization will be crucial in this role. **Key Responsibilities:** - Develop cutting-edge DFT tools to enhance the MODUS software product - Design and verify RTL and test benches - Provide support to application and product engineers - Enhance usability and quality through feature enhancement and rigorous verification - Offer R&D support, problem analysis, debugging, and develop new features to optimize synthesis results for timing, area, and power **Qualifications Required:** - M.Tech, M.E, B.Tech, or B.E. in EE/ECE/CS or equivalent - Good understanding of Digital Electronics - Prior knowledge of Verilog/System Verilog and EDA tools - Proficiency in RTL design using Verilog and SystemVerilog - Familiarity with front-end EDA tools, SystemVerilog assertions, and advanced verification techniques - Knowledge of scripting languages like Perl or Python, DFT methodologies, and synthesis tools - Strong foundation in data structures and algorithms Cadence values innovation and research, offering mentoring and support to enhance your problem-solving skills. Join Cadence to work on impactful projects and tackle challenges that others can't.,