DFT Lead Engineer ASIC/SoC

Talenton Technology Services

10 - 18 years

40 - 90 Lacs

bengaluru

Posted:-1 days ago| Platform:

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Skills Required

vlsi soc asic dft automotive soc semiconductor spyglass dft tapeout mbist boundary scan mentor iso 26262 perl jtag design-for-test atpg tessent dftmax lbist scan tcl synopsys siemens eda python

Work Mode

Work from Office

Job Type

Full Time

Job Description

DFT Lead Engineer ASIC/SoC

About the Company:

4D LiDAR technology

Role Overview:

DFT Lead Engineer

Key Responsibilities:

Define, develop, and implement
DFT methodologies
for complex SoC/ASIC designs.
Own
DFT planning, insertion, verification, and validation
at block and top level.
Collaborate with
RTL, Physical Design, and ASIC vendors
to ensure full test coverage for automotive-grade silicon.
Integrate and verify IP-level DFT implementation across the SoC.
Support
post-silicon bring-up, debug, failure analysis, and yield improvement
.
Maintain
DFT documentation, test guidelines, and architecture specs
.

Required Skills and Experience:

12+ years
of experience developing and implementing DFT architecture for complex ASIC/SoC designs.
Deep expertise in
SCAN/ATPG, MBIST/LBIST, JTAG (IEEE 1149.x/1500/1687), Boundary Scan
, and compression/decompression methods.
Proficiency with
Mentor Tessent
or
Synopsys DFTMAX
tool suites.
Hands-on scripting skills (
Python, Perl, TCL
) for automation.
Strong understanding of
RTL coding
,
DFT constraints (SDC)
, and design flows.
Recent
tape-out experience
at advanced technology nodes (7 nm or below preferred).

Nice to Have:

Experience with
automotive-grade SoCs
, AEC-Q100 qualification, or
ISO 26262
compliance.
Familiarity with
mixed-signal DFT
and
analog test strategies
.
Exposure to
post-silicon validation
and
diagnostic firmware
development.

Education:

Electronics, Electrical, or VLSI Design Engineering

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