10 Lbist Jobs

Works independently with minimal supervision. Provides supervision/guidance to other team members. Having strong decision making and technical leadership skills. Having good verbal and written communication skills to convey complex information.

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementation and feature insertion for complex SoCs. Implement Scan Insertion , ATPG , Compression , MBIST , and Boundary Scan (JTAG) . Work with Mentor Graphics, Synopsys , or Cadence DFT tools for flow execution and verification. Generate and validate test vectors , support simulation, and ensure fault coverage goals. Assist with DFT verification , timing closure support , and pre-silicon checks . Collaborate with RTL, PD, and STA teams during integration and tape-out phases. Automate DFT flows using Tcl , Perl , or other scripting tools to improve efficiency. Contribute to post-silicon bring-up and production test debugging , where applicable. Work under the guidance of technical leads while also mentoring junior team members when needed. Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics , Electrical Engineering , or a related discipline. 4–8 years of hands-on DFT experience in SoC/ASIC environments. Practical knowledge of: Scan/Compression Insertion and ATPG MBIST architectures and memory BIST flows Boundary Scan (JTAG / IEEE 1149.x) Exposure to silicon bring-up or production test is a strong advantage. Scripting experience using Tcl, Perl , or similar languages. Strong debugging, documentation, and collaboration skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Experience (years) : 5+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 5+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 9+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.