17 Lbist Jobs

As a member of the team at Cadence, your role will involve: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will be part of a team that is focused on doing work that matters and solving challenges that others may find difficult. Join us in making an impact on the world of technology.,

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

You have a great opportunity as a DFT Lead Engineer with 6+ years of experience at a work location in Bangalore or Hyderabad. As a DFT Lead Engineer, you will be responsible for the DFT implementation of the latest products, including scan insertion, ATPG, LBIST, and MBIST. Your role will involve verifying the DFT implementation and delivering test patterns for production testing. Additionally, you will support Silicon bring-up activities to ensure the highest stability of the test pattern. In this position, you will contribute to the overall microcontroller DFT methodology and coordinate DFT work packages. You will be required to engage in hands-on work, provide status reports, and collaborate with project management, layout team, and test engineering. Proficiency with Synopsys tools such as TetraMAX, Verdi, and DFT Compiler is essential for this role. The ideal candidate should have a solid understanding of scan chains, stuck-at/fault models, and test coverage. If you are looking for a challenging role that allows you to showcase your DFT expertise and work on cutting-edge technologies, this position is perfect for you.,

Role & responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Preferred candidate profile Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Cando attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

We are looking for skilled DFT Engineers with hands-on experience in RTL coding, scan insertion, ATPG, and coverage analysis to join our semiconductor engineering team. Key Responsibilities: Perform scan insertion, JTAG, ATPG DRC, and coverage analysis. Debug simulation with timing/SDF and root cause failures. Work on LBIST and Mixed Signal Radar ICs. Collaborate closely with design and verification teams. Ensure quality deliverables with proactive and detail-oriented work. Key Skills: Verilog / VHDL RTL coding Mentor DfT Tools, Cadence Tools Scan Insertion, JTAG, ATPG, Coverage Analysis LBIST, Mixed Signal Radar ICs (Preferred) Simulation Debug with Timing/SDF Soft Skills: Strong interpersonal and communication skills Proactive, collaborative, and self-motivated Ability to work independently and in a team

You will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. This includes designing and implementing RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Your role will also involve owning, maintaining, extending, and enhancing existing DFT IP like LBIST. At Cadence, we are focused on hiring and developing leaders and innovators who are passionate about making an impact on the world of technology. Join us in our mission to solve challenges that others cannot.,

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mentor) is a plus Knowledge on Spyglass-DFT Excellent hands-on debug skills and scripting skills are critical Knowledge on automation scripts like TCL/AWK/SED is a plus Understands the basics of JTAG Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Works independently with minimal supervision. Provides supervision/guidance to other team members. Having strong decision making and technical leadership skills. Having good verbal and written communication skills to convey complex information.

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementation and feature insertion for complex SoCs. Implement Scan Insertion , ATPG , Compression , MBIST , and Boundary Scan (JTAG) . Work with Mentor Graphics, Synopsys , or Cadence DFT tools for flow execution and verification. Generate and validate test vectors , support simulation, and ensure fault coverage goals. Assist with DFT verification , timing closure support , and pre-silicon checks . Collaborate with RTL, PD, and STA teams during integration and tape-out phases. Automate DFT flows using Tcl , Perl , or other scripting tools to improve efficiency. Contribute to post-silicon bring-up and production test debugging , where applicable. Work under the guidance of technical leads while also mentoring junior team members when needed. Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics , Electrical Engineering , or a related discipline. 4–8 years of hands-on DFT experience in SoC/ASIC environments. Practical knowledge of: Scan/Compression Insertion and ATPG MBIST architectures and memory BIST flows Boundary Scan (JTAG / IEEE 1149.x) Exposure to silicon bring-up or production test is a strong advantage. Scripting experience using Tcl, Perl , or similar languages. Strong debugging, documentation, and collaboration skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Role & responsibilities • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Preferred candidate profile Immediate joining