3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a DFT Engineer at Google, you will play a key role in developing custom silicon solutions for Google's direct-to-consumer products. Your expertise in DFT methodologies and Electronic Design Automation (EDA) tools like Tessent will contribute to the innovation and performance of products used by millions worldwide. Working closely with RTL and Physical Designer Engineers, you will help shape the next generation of hardware experiences. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage and power domains. You will also be involved in writing basic scripts to automate the DFT flow and developing tests for production in the Automatic Test Equipment (ATE) flow. To be successful in this role, you should have a Bachelor's degree in Electrical or Electronics Engineering, along with at least 3 years of experience in DFT methodologies. Experience in areas such as ATPG, Low Power designs, BIST, JTAG, and IJTAG tools and flow will be beneficial. Preferred qualifications include experience in architecting/developing DFT flows and methodologies, as well as collaborating with Design, Physical Design (PD), and Static Timing Analysis (STA) teams. Strong scripting skills in languages like Python and TCL are also desired. Join us in our mission to organize the world's information and create helpful experiences for users through innovative hardware technologies. Your contributions will play a vital role in making people's lives better through technology.,

Posted 3 weeks ago

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ASIC DFT Engineering Technical Leader - DFT Cisco

10.0 - 14.0 years

0 Lacs

karnataka

On-site

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

Posted 4 weeks ago

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VLSI MBIST Engineer Coventine Digital

4.0 - 8.0 years

5 - 15 Lacs

Bengaluru

Work from Office

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

Posted 1 month ago

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