6 Tapeout Jobs

Axiado is an AI-enhanced security processor company that is revolutionizing the control and management of digital systems. Founded in 2017, Axiado currently has a team of over 100 employees who are dedicated to developing cutting-edge technology. At Axiado, we believe that exceptional results are achieved through collaboration, respect, and going the extra mile. If you are passionate about disrupting the status quo, driving innovation, and making a difference in the world, we encourage you to apply for the following position. The ASIC/SoC Design position at Axiado offers you the opportunity to be part of a leading company in Smart Edge SoCs for network/systems control, management security systems, and IIoT. As an ASIC/SoC Design Engineer, you will be involved in all aspects of the SoC design flow, working closely with various teams and reporting to the Director of Engineering. **KEY RESPONSIBILITIES** - Developing the design and implementation of SoCs. - Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks. - Performance, bandwidth, and power optimization at both top-level and block-level. - Collaborating with FPGA engineers for early prototyping. - Supporting test program development, chip validation, and chip life until production maturity. - Working with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout different stages of ASIC development. **Qualifications** - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. - Proficiency in writing clear micro-architecture specifications and efficient RTL code in Verilog. - Knowledge of assertions, coverage analysis, RTL synthesis, and timing closure. - Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Design bring up and debug experience on FPGA-based emulation platforms. - Proficiency in scripting languages such as Perl and Python. - Previous tapeout experience is a must. - Silicon bring-up and debug experience (Preferred). - Familiarity with repository management tools like Bitbucket/Jenkins and bug tracking tools like JIRA. Axiado is dedicated to attracting, developing, and retaining top talent in a diverse and dynamic environment. Headquartered in Silicon Valley, we have access to leading research, technology, and talent. We are focused on building a team that is committed to securing every node on the internet and solving real-world problems. We value persistence, intelligence, curiosity, hard work, continuous learning, and mutual support in our team members.,

Postition Summary This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 6-8 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readout Relevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required. Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forzas history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industrys largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com AMETEK, Inc. is a leading global provider of industrial technology solutions serving a diverse set of attractive niche markets with annual sales over $7.0 billion. AMETEK is committed to making a safer, sustainable, and more productive world a reality. We use differentiated technology solutions to solve our customers most complex challenges. We employ 21,000 colleagues, in 35 countries, that are grounded by our core values: Ethics and Integrity, Respect for the Individual, Inclusion, Teamwork, and Social Responsibility. AMETEK (NYSE:AME) is a component of the S&P 500. Visit www.ametek.com for more information. Show more Show less

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well as optimizing layouts for performance, area, and reliability across PVT corners. Additionally, you will support tape-out and post-layout verification activities, participate in design reviews, and maintain proper documentation of layout guidelines and review skills. You should have proven experience in custom analog layout for high-speed and precision circuits, a strong working knowledge of FinFET nodes, proficiency in layout tools like Cadence Virtuoso and Calibre, and sound knowledge of DRC, LVS, and EMIR verification methodologies. Understanding of layout effects such as matching, shielding, symmetry, and noise isolation, as well as familiarity with EDA scripting (Skill, Tcl, Python), will be beneficial. Strong problem-solving skills, attention to detail, and good communication and collaboration abilities in a team-based environment are essential for success in this role. Join us to work on cutting-edge layout challenges with the latest process technologies and be a part of a fast-growing semiconductor team working on impactful silicon designs. Competitive compensation and career development opportunities await you in this exciting opportunity.,

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floorplanning is a plus. Show more Show less

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

What You'll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You'll Need: Bachelor's or master's degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus.