20 Tapeout Jobs

As a Director of Physical Design at Tecquire Solutions Private Limited, you will play a crucial role in leading and growing the physical design team to implement complex SoC and ASIC designs effectively. Your responsibilities will include: - Leading and managing the entire Physical Design team across multiple projects and geographies. - Driving end-to-end physical implementation including RTL handoff, floorplanning, place & route, clock tree synthesis, static timing analysis, physical verification (DRC/LVS), and tape-out. - Owning project planning, resource allocation, schedule management, and risk mitigation across multiple physical design programs. - Collaborating with cross-functional tea...

As a Physical Verification Engineer for SOC/blocks, your role will involve the following key responsibilities: - Conduct physical verification for SOCs, cores, and blocks, encompassing tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. - Tackle critical design and execution challenges related to physical verification and sign-off. - Possess a thorough understanding of physical verification and sign-off workflows and methodologies. - Collaborate with PNR engineers to attain sign-off at different stages of the design process. To excel in this role, you should have the following qualifications and skills: - Proficiency in physical verification for SoC/full-chip and block-level proces...

Role Overview: As a Design Verification Engineer at Architect Labs, you'll redefine the hardware design and verification process, methodology, and tools using proprietary AI models and systems. You will be responsible for building and curating high-quality RTL and verification datasets for AI training and evaluation. Your tasks will include working on test-benches, coverage analysis, assertion coding, debug-friendly measurements, curation, and labeling of AI-generated collateral. Key Responsibilities: - Create detailed test plans based on design specifications - Specify and build a UVM-based validation infrastructure for POC designs - Develop directed and random test cases to thoroughly test...

Experience : 3.00 + years Salary : INR 2680000-3750000 / year (based on experience) Expected Notice Period : 15 Days Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs) (*Note: This is a requirement for one of Uplers client - Architect Labs) What do you need for this opportunity Must have skills required: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration Architect Labs is Looking for: We are an AI research and product lab for chip design. Our goal is to redefine the hardware design an...

As a member of the Cisco SiliconOne team, you will play a crucial role in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by working on complex chips for various aspects of systems and applications. You will have the opportunity to work on Silicon, Hardware, Software, telemetry, security, and more, gaining exposure to all facets of the development process. The team offers a unique blend of a startup culture within the framework of a top-tier networking company. **Key Responsibilities:** - Utilize your ASIC design expertise to contribute to the development cycle from specification to tape-out and lab validation - Demonstrate proficiency in RTL design, including archi...

As a Digital Physical Design Engineer (G2) at our company, your role will involve contributing to the physical implementation of complex digital integrated circuits. You will work on various stages of the physical design flow, from synthesis to tape-out, ensuring that performance, power, and area targets are met. **Key Responsibilities:** - Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). - Perform physical verification (DRC, LVS, Antenna) and resolve related issues. - Conduct power integrity analysis (IR drop, EM) and optimize designs for power efficiency. - Participate in design-for-test (DF...

As an Engineer with 5+ years of experience in the Physical Design Domain with flow tracer experience, your role will involve guiding the team, analyzing and documenting issues, providing fixes, and tracking milestones. You will also be expected to have basic experience in analyzing calibre reports. Key Responsibilities: - Guide the team, either as a sub-lead or lead based on experience. - Analyze and document issues, providing necessary fixes. - Track project milestones effectively. - Analyze calibre reports to ensure quality standards. Qualifications: - 5+ years of experience as a Physical Design Engineer. - Bachelor's or Master's degree in a related field. - Proficiency in Digital Electron...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routability analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routablity analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes, ...

DFT Lead Engineer ASIC/SoC About the Company: Aevas mission is to bring the next wave of perception to a broad range of applications — from automated driving to industrial robotics, consumer electronics, and beyond. Aeva’s groundbreaking 4D LiDAR technology integrates key LiDAR components onto a single silicon photonics chip, enabling devices to sense both position and instant velocity for safer, smarter decision-making. Role Overview: As a DFT Lead Engineer , you will define, develop, and optimize Design-For-Test architecture for Aeva’s high-performance LiDAR SoCs . You’ll own the end-to-end DFT strategy — from planning and insertion to verification, silicon bring-up, and yield improvement....

In a fast-paced leading-edge design environment with endless possibilities of innovation and learning, you will be responsible for ensuring flawless execution in specific areas of SoC level Physical Design such as Physical Verification, Tapeout, ESD Verification, and Pre-emptive Quality audits of incoming designs. This is a great opportunity to join a team of talented individuals working on state-of-the-art complex SoC Designs as part of Intel Foundry Design Services and Reference Design Development teams. - Integration and generation of layout and netlist views of different levels of hierarchy up to SoC. - Layout verification and signoff for IP blocks, APR partition, and SoC levels of hiera...

Postition Summary This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work...

As an experienced Physical Design Engineer, you will be responsible for executing block level P&R and Timing closure activities. Your primary role will involve owning up block level P&R and performing Netlist2GDS on blocks. You will be working on the implementation of multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. Your expertise should cover various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal I...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

Axiado is an AI-enhanced security processor company that is revolutionizing the control and management of digital systems. Founded in 2017, Axiado currently has a team of over 100 employees who are dedicated to developing cutting-edge technology. At Axiado, we believe that exceptional results are achieved through collaboration, respect, and going the extra mile. If you are passionate about disrupting the status quo, driving innovation, and making a difference in the world, we encourage you to apply for the following position. The ASIC/SoC Design position at Axiado offers you the opportunity to be part of a leading company in Smart Edge SoCs for network/systems control, management security sy...

Postition Summary This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of t...

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and ...

What You'll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog a...