This is a great opportunity to work as a part of a highly regarded team to deliver leading-edge solutions. We are looking for an experienced engineer for an exciting role to augment our core Linux embedded team and work on the latest platforms and software. You will have the chance to interact closely with key technical experts to ensure the best possible performance and results on the SoC platforms. Your responsibilities will include embedded Linux software apps/drivers or kernel development, porting, customization, performance benchmarking, and optimization. You will collaborate with the team on building and supporting system software subsystems, as well as own system software development and debugging. Additionally, you will be involved in the implementation of functional safety features for embedded platforms. Key qualifications for this role include strong C/C++ development skills with a good understanding of object-oriented design, a solid background in microprocessor/microcontroller/DSP-based embedded systems development, and experience dealing with the Linux community and open-source contribution. You should possess system knowledge, system debugging skills, and strong written and verbal communication abilities. Being self-motivated and able to take the lead in mastering new technologies is essential, as well as the ability to work both independently and as part of a team. Furthermore, you will be responsible for testing developed modules by running tests and providing regular progress reports to various stakeholders involved. Preferred qualifications for this role include experience in FPGA-based system development, knowledge of RISC-V processors, and functional safety certification. If you are a passionate engineer with the above qualifications and ready to take on new challenges in the field of embedded systems development, we encourage you to apply for this exciting opportunity.,
As the Lead for the implementation of Ceremorphic AI hardware architecture and design of memory technologies, you will play a crucial role in integrating knowledge from various fields like AI, compilers, computer architecture, analog circuits, and memories. Your responsibilities will revolve around designing memory technologies including SRAM, Register Files, ROM generators, and other related components. Your key requirements for this position include a fundamental understanding of bit cell characteristics such as SNM, WM, Cell current, Standby current, data retention, among others. You should also possess expertise in dealing with process variability and circuit reliability issues that impact power consumption, speed, area utilization, and yield. A strong grasp of custom circuit design and layout in finFET-based CMOS technologies is essential for success in this role. Additionally, you are expected to have proficiency in critical path modeling using various models like RC, C, Pi, ladder, distributive, and others. Familiarity with scripting languages such as Python or Perl, as well as the UNIX operating system, will be beneficial. Demonstrated technical leadership skills and a solid foundation in semiconductor physics are also crucial. Moreover, a good understanding of semiconductor physics, along with knowledge and interest in IC technology and IP design, is mandatory for this position. Your ability to lead and drive the implementation of cutting-edge memory technologies within the Ceremorphic AI hardware framework will be pivotal in advancing the company's technological capabilities.,
The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST, and ATPG, strong background in TCL/Perl programming, and expertise in double patterning process nodes are required. Preferably, expertise in Cadence RTL-to-GDSII flow is also desired.,