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4.0 - 8.0 years
0 Lacs
karnataka
On-site
Job Description You are required to be an experienced DFT Engineer with a strong background in Scan, ATPG, and MBIST for SoC/ASIC designs. Your main responsibilities will include implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key Responsibilities - Implement and verify Scan, ATPG, and MBIST for complex SoCs. - Perform pattern generation, coverage analysis, and debug. - Integrate and validate MBIST with appropriate memory test algorithms. - Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff. - Develop automation scripts to streamline DFT flows. Qualification Required - Minimum 4 years o...
Posted 1 day ago
5.0 - 9.0 years
0 Lacs
karnataka
On-site
You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...
Posted 2 months ago
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