12 Fault Models Jobs

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon, system, and software design services, including digital and analog design and project management Position: DFT Lead - P-MBIST Location: Remote Job Type: Full time Job Description: A senior DFT specialist who can take full ownership of PMBIST planning, insertion, verification, and closure. Someone whos comfortable running end-to-end DFT flows, debugging patterns, and driving coverage targets with minimal supervision. Key Skills required: PMBIST architecture, integration, and ver...

NextSilicon is reimagining high-performance computing by leveraging intelligent adaptive algorithms to vastly accelerate supercomputers and drive them into a new generation. The new software-defined hardware architecture enables high-performance computing to fulfill its promise of breakthroughs in advanced research fields. NextSilicon's core values include: - Professionalism: Striving for exceptional results through professionalism and unwavering dedication to quality and performance. - Unity: Fostering a collaborative work environment where every employee feels valued and heard. - Impact: Passionate about developing technologies that make a meaningful impact on industries, communities, and ...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will play a crucial role in the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your tasks will involve defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team at AMD that delivers cutting-edge IPs essential for every SOC. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX fe...

Introduction As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market. We are looking for a DFT lead to join our dynamic team and drive excellence in chip test strategies, design and testability. Your Role And Responsibilities We are seeking highly motivated DFT Engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation and delivery of DFT patterns for IBM's chip design team. As a member of DFT team,...

Job Description You are required to be an experienced DFT Engineer with a strong background in Scan, ATPG, and MBIST for SoC/ASIC designs. Your main responsibilities will include implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key Responsibilities - Implement and verify Scan, ATPG, and MBIST for complex SoCs. - Perform pattern generation, coverage analysis, and debug. - Integrate and validate MBIST with appropriate memory test algorithms. - Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff. - Develop automation scripts to streamline DFT flows. Qualification Required - Minimum 4 years o...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

As a PMTS SILICON DESIGN ENGINEER at AMD, you will play a crucial role in developing and implementing advanced DFT IP and design methodologies for complex SoCs/ASICs. Your deep technical expertise in DFT architecture and strong leadership skills will be essential in driving execution, mentoring engineers, and ensuring high-quality, testable designs. Here's what you will be responsible for: - **Team Leadership & Management** - Lead and mentor a team of DFX engineers, fostering technical excellence, innovation, and collaboration. - Manage project priorities, schedules, and deliverables to meet program milestones. - Recruit, train, and develop engineering talent. - **DFT Strategy & Execution** ...

As a DFT Technical Manager at NextSilicon, you will play a crucial role in the DFT implementation of the company's next SOC. Your primary focus will be on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. Your responsibilities will include developing DFT flow/methodologies, managing a team of 3-4 DFT engineers, and ensuring thorough testing and fault coverage alignment with industry standards. **Role Overview:** NextSilicon is reimagining high-performance computing with accelerated compute solutions and a software-defined hardware architecture. As a DFT Technical Manager, ...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs....

You have a great opportunity as a DFT Lead Engineer with 6+ years of experience at a work location in Bangalore or Hyderabad. As a DFT Lead Engineer, you will be responsible for the DFT implementation of the latest products, including scan insertion, ATPG, LBIST, and MBIST. Your role will involve verifying the DFT implementation and delivering test patterns for production testing. Additionally, you will support Silicon bring-up activities to ensure the highest stability of the test pattern. In this position, you will contribute to the overall microcontroller DFT methodology and coordinate DFT work packages. You will be required to engage in hands-on work, provide status reports, and collabor...

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention...