14 Dft Techniques Jobs

As a Physical Design Engineer at Kinara, you will play a crucial role in the development of complex data path and control blocks. Your responsibilities will include: - Developing new techniques and flows to rapidly prototype hardware blocks. - Implementing flows that allow for detailed power estimation. - Collaborating with the design team to understand placement and recommend implementation options. - Engaging with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include: - BTech/MTech EE/CS with 8+ years of Physical Design experience. - Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout t...

As a DFT Technical Manager at NextSilicon, you will play a crucial role in the DFT implementation of the company's next SOC. Your primary focus will be on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. Your responsibilities will include developing DFT flow/methodologies, managing a team of 3-4 DFT engineers, and ensuring thorough testing and fault coverage alignment with industry standards. **Role Overview:** NextSilicon is reimagining high-performance computing with accelerated compute solutions and a software-defined hardware architecture. As a DFT Technical Manager, ...

As a Product Validation Engineer at Cadence Design Systems, you will be a crucial part of the Modus R&D team, focusing on validating and supporting Design-for-test (DFT) technologies. Your role will involve working on complex problems that require innovative thinking, debugging customer reported issues, and collaborating with R&D to provide out-of-box solutions with an emphasis on robustness, PPA, and scalability. **Key Responsibilities:** - Work on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST, etc., using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer design...

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure hi...

At Allegion, we are dedicated to ensuring the safety and security of the people you care about in their residential, commercial, and public environments. Our global presence, with over 30 brands, 12,000+ employees, and products available in 130 countries, focuses on security solutions for doorways and beyond. Allegion India, located in Bangalore, serves as the Engineering and Technology hub, boasting a talented pool of over 600 dedicated professionals. Our product development process involves collaboration among different engineering groups, starting from product requirements, mechanical and electronics systems, mobile and cloud integrations, to rigorous validation before market release. As ...

At Cadence, we are constantly seeking talented and motivated individuals to join our team and contribute to the ever-evolving world of technology. As part of the Modus R&D team at Cadence Design Systems, we are currently looking for an engineer who is passionate about validating and supporting Design-for-test (DFT) technologies. The ideal candidate should have a minimum of 2 years of experience in DFT/ATPG/ASIC Design flows, along with a solid understanding of RTL Verilog/VHDL coding styles and Synthesis. In this role, you will be responsible for working on complex problems that require innovative thinking and collaborating with various teams to propose out-of-box solutions focusing on robus...

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: SoC Design and Microarchitecture Lead Translate high level SoC architecture to microarchitecture details to help SoC implementation and verification Expertise in SoC Chip Pervasive Logic Cl...

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. We are seeking a highly experienced and motivated DFT (Design for Testability) Lead to join our dynamic team, with a strong background in implementing and managing DFT methodologies. The DFT Lead will be responsible for leading a team of engineers to develop and execute DFT strategies that ensure the highest level of product quality and reliability. Responsibilities Lead the design and implementation of advanced DFT architectures and methodol...

Are you seeking an exciting career opportunity at one of the world's leading semiconductor companies Texas Instruments (TI) is inviting applications for the position of Senior Analog Design Engineer. As part of a dedicated team of engineers, you will be involved in developing highly complex mixed signal devices for audio applications, showcasing industry-leading performance. This role offers a unique chance to join an established team that is continuously seeking growth opportunities. You will collaborate with top-tier customers globally and contribute to the development of cutting-edge solutions in consumer electronics, industrial, and automotive markets. As a prospective candidate, you sho...

You will be part of Kinara, a Bay Area-based venture backed company, founded based on research conducted at Stanford University. Kinara's game-changing AI solutions aim to revolutionize what individuals and businesses can accomplish. Their Ara inference processors, combined with an innovative SDK, offer unparalleled deep learning performance at the edge. This enables the acceleration and optimization of real-time decision-making, emphasizing the importance of speed and power efficiency. By embedding high-performance AI into edge devices, Kinara contributes to creating a smarter, safer, and more enjoyable world. As the field of Edge AI is on the verge of a significant growth phase, Kinara is ...

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture ...

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Pe...

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure hi...